MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 285

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out
period. A premature write the CRG will immediately generate a reset.
As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock
monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching
the COP vector.
9.5.3
The on-chip voltage regulator detects when V
on reset or low voltage reset or both. As soon as a power-on reset or low voltage reset is triggered the CRG
performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid
oscillator clock signal the reset sequence starts using the oscillator clock. If after 50 check windows the
clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock mode.
Figure 9-26
and when the RESET pin is held low.
Freescale Semiconductor
Power-On Reset, Low Voltage Reset
and
Figure 9-27
Internal RESET
RESET
Internal POR
Internal RESET
RESET
Internal POR
Figure 9-26. RESET Pin Tied to V
show the power-up sequence for cases when the RESET pin is tied to V
Figure 9-27. RESET Pin Held Low Externally
MC9S12C-Family / MC9S12GC-Family
DD
Clock Quality Check
(no Self-Clock Mode)
Clock Quality Check
(no Self-Clock Mode)
to the MCU has reached a certain level and asserts power-
Rev 01.24
128 SYSCLK
) (
) (
128 SYSCLK
) (
) (
) (
) (
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
64 SYSCLK
DD
64 SYSCLK
(by a Pull-Up Resistor)
DD
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