MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 165
MC9S12C128VFU
Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12C128VFU.pdf
(690 pages)
Specifications of MC9S12C128VFU
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Chapter 6
Background Debug Module (BDMV4) Block Description
6.1
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12
core platform.
A block diagram of the BDM is shown in
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
BDMV4 has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake
signal to indicate when an operation is complete. The system is backwards compatible with older external
interfaces.
6.1.1
Freescale Semiconductor
•
•
•
•
•
•
Single-wire communication with host development system
BDMV4 (and BDM2): Enhanced capability for allowing more flexibility in clock rates
BDMV4: SYNC command to determine communication rate
BDMV4: GO_UNTIL command
BDMV4: Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single-chip mode
Introduction
Features
SYSTEM
HOST
BDMACT
ENBDM
ENTAG
TRACE
SDV
BKGD
16-BIT SHIFT REGISTER
INSTRUCTION DECODE
MC9S12C-Family / MC9S12GC-Family
Figure 6-1. BDM Block Diagram
AND EXECUTION
STANDARD BDM
LOOKUP TABLE
FIRMWARE
Figure
Rev 01.24
6-1.
CONTROL LOGIC
BUS INTERFACE
CLKSW
AND
ADDRESS
DATA
CLOCKS
165
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