MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 85

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

2.3.2.2
2.3.2.2.1
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The SCI port associated with transmit pin 1 is configured as output if the transmitter is enabled and the
SCI pin associated with receive pin 0 is configured as input if the receiver is enabled. Please refer to SCI
Block User Guide for details.
2.3.2.2.2
Read: Anytime.
Write: Never, writes to this register have no effect.
Freescale Semiconductor
Module Base + 0x0008
Module Base + 0x0009
PTIS[3:0]
Reset
Reset
Field
3–0
SCI
W
W
R
R
Port S Input Register — This register always reads back the status of the associated pins. This also can be
used to detect overload or short circuit conditions on output pins.
Port S Registers
—
0
0
0
0
7
7
Port S I/O Register (PTS)
Port S Input Register (PTIS)
= Unimplemented or Reserved
= Unimplemented or Reserved
—
0
0
0
0
6
6
Figure 2-11. Port S Input Register (PTIS)
Figure 2-10. Port S I/O Register (PTS)
Table 2-10. PTIS Field Descriptions
MC9S12C-Family / MC9S12GC-Family
—
0
0
0
0
5
5
Rev 01.24
—
0
0
0
0
4
4
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
PTIS3
PTS3
—
0
0
3
3
PTIS2
PTS2
—
0
0
2
2
PTIS1
PTS1
TXD
0
0
1
1
PTIS0
PTS0
RXD
0
0
0
0
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