MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 269

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

9.4.2
The clock generator creates the clocks used in the MCU (see
top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting
of the respective configuration bits.
The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The
memory blocks use the bus clock. If the MCU enters self-clock mode (see
Mode”), oscillator clock source is switched to PLLCLK running at its minimum frequency f
clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU.
The core clock is twice the bus clock as shown in
one bus clock.
PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned
off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum
Freescale Semiconductor
EXTAL
XTAL
System Clocks Generator
OSCILLATOR
Condition
Gating
PHASE
LOCK
LOOP
= Clock Gate
OSCCLK
PLLCLK
Monitor
Clock
Figure 9-17. System Clocks Generator
MC9S12C-Family / MC9S12GC-Family
PLLSEL or SCM
1
0
1
0
SCM
Rev 01.24
Figure
STOP(PSTP,PCE),
STOP(PSTP,PRE),
WAIT(COPWAI),
WAIT(SYSWAI),
WAIT(RTIWAI),
WAIT(SYSWAI),
STOP(PSTP)
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
COP enable
RTI enable
STOP
STOP
9-18. But note that a CPU cycle corresponds to
SYSCLK
Figure
9-17). The gating condition placed on
WAIT(CWAI,SYSWAI),
÷2
Section 9.4.7.2, “Self-Clock
STOP
CLOCK PHASE
GENERATOR
COP
RTI
SCM
Pseudo-Stop Mode
(running during
Core Clock
Bus Clock
. The bus
Oscillator
Oscillator
Clock
Clock
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