MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 466
MC9S12C128VFU
Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12C128VFU.pdf
(690 pages)
Specifications of MC9S12C128VFU
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Chapter 16 Dual Output Voltage Regulator (VREG3V3V2) Block Description
16.2.3
Signals V
logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF,
X7R ceramic).
In Shutdown Mode an external supply at V
16.2.4
Signals V
PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In Shutdown Mode an external supply at V
16.2.5
This optional signal is used to shutdown VREG3V3V2. In that case V
be provided externally. Shutdown Mode is entered with V
VREG3V3V2 is either in Full Performance Mode or in Reduced Power Mode.
For the connectivity of V
16.3
This subsection provides a detailed description of all registers accessible in VREG3V3V2.
16.3.1
Figure 16-2
466
DDPLL
DD
Memory Map and Register Definition
Address
0x0000
Offset
V
V
V
Module Memory Map
provides an overview of all used registers.
/V
DD
DDPLL
REGEN
Switching from FPM or RPM to shutdown of VREG3V3V2 and vice versa
is not supported while the MCU is powered.
SS
/V
, V
are the primary outputs of VREG3V3V2 that provide the power supply for the core
SSPLL
SS
, V
— Optional Regulator Enable
— Regulator Output1 (Core Logic)
are the secondary outputs of VREG3V3V2 that provide the power supply for the
SSPLL
REGEN
see device overview chapter.
— Regulator Output2 (PLL)
VREG3V3V2 Control Register (VREGCTRL)
Table 16-2. VREG3V3V2 Memory Map
MC9S12C-Family / MC9S12GC-Family
DD
DDPLL
/V
Rev 01.24
SS
NOTE
/V
Use
can replace the voltage regulator.
SSPLL
REGEN
can replace the voltage regulator.
being low. If V
DD
/V
SS
and V
REGEN
Freescale Semiconductor
DDPLL
is high, the
Access
R/W
/V
SSPLL
must
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