MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 413
MC9S12C128VFU
Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12C128VFU.pdf
(690 pages)
Specifications of MC9S12C128VFU
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Chapter 14
Serial Peripheral Interface (SPIV3) Block Description
14.1
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
14.1.1
The SPIV3 includes these distinctive features:
14.1.2
The SPI functions in three modes, run, wait, and stop.
This is a high level description only, detailed descriptions of operating modes are contained in
Section 14.4, “Functional Description.”
Freescale Semiconductor
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Master mode and slave mode
Bidirectional mode
Slave select output
Mode fault error flag with CPU interrupt capability
Double-buffered data register
Serial clock with programmable polarity and phase
Control of SPI operation during wait mode
Run Mode
This is the basic mode of operation.
Wait Mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI
clock generation turned off. If the SPI is configured as a master, any transmission in progress stops,
but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
Stop Mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI
is configured as a slave, reception and transmission of a byte continues, so that the slave stays
synchronized to the master.
Introduction
Features
Modes of Operation
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
413
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