SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 107

• Manufacturer Part Number: SAA7146AH/V4,557
• Description: IC VIDEO SPCI BRIDGE HP 160-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Bridger

Specifications of SAA7146AH/V4,557

• Package / Case: 160-QFP
• Applications: DTV
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1318; 935269343557; SAA7146AHBB

Philips Semiconductors
7.16.4.1
The clock divider circuit offers 16 different clock stages.
To transform a reference clock of 24.576 MHz to a bit clock
for an 8 kHz and 8-bit sampling (just 8-bit serial), a clock
division of 384 has to be selected. To transform a
reference clock of 24.576 MHz to a bit clock for a 48 kHz
sampling and 64-bit framing, a division of 8 has to be
selected.
The bit clock is divided by 8, which defines a time slot
corresponding to the time span of one byte in serial
protocol.
The time slot counter gets a count pulse every time slot.
It can be running free or can be triggered (reset) via an
external word select signal (super frame sync).
2004 Aug 25
handbook, full pagewidth
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Audio clock selection
EOS1
TSL1
WS0
A1
BCLK1
COUNTER 1
A1
DIVIDER 1
SOURCE
SELECT
SLOT
ACLK
ACLK
TIME
CLK
1/8
A1
Fig.38 Audio clock control.
BCLK1
BCLK1_OEN
107
Audio interface circuit A1 can be triggered by WS0, audio
interface circuit A2 can be triggered by WS4. A time slot
list processor generates word select output signals and the
internal signals to control the signal flow per time slot.
A time slot list contains up to 16 records, each 32 bits
wide, supporting super frames with up to 32 time slots.
WS0 (or WS4) triggers the time slot generator and time
slot counter directly ‘in sync’ or are one clock cycle ahead.
The WS signals can be generated ‘in sync’ with the time
slot (i.e. MSB of serial data) or 1-bit clock cycle ahead.
Each of the two audio interface circuits A1 and A2 has its
own independent timing generator. Extra control bits
define which of the two timing generators drive which of
the word select pins WS0 to WS4.
BCLK2
BCLK2_OEN
COUNTER 2
DIVIDER 2
SOURCE
SELECT
SLOT
ACLK
ACLK
TIME
CLK
1/8
A2
BCLK2
A2
MGG281
TSL2
WS4
A2
EOS2
Product specification
SAA7146A