SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 35

• Manufacturer Part Number: SAA7146AH/V4,557
• Description: IC VIDEO SPCI BRIDGE HP 160-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Bridger

Specifications of SAA7146AH/V4,557

• Package / Case: 160-QFP
• Applications: DTV
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1318; 935269343557; SAA7146AHBB

Philips Semiconductors
7.4.4.10
The Load Register (LDREG) command has a variable
Dword count specified by the Block_length. It is at least
two Dwords long and at maximum 256 Dwords.
The LDREG command interprets the following Dwords as
data and writes it to the registers beginning at the specified
register address (D6 to D0).
The Store Register (STREG) command is a two Dword
command. It transfers the contents of the addressed
(D6 to D0) SAA7146A register into PCI memory that is
addressed by interpreting the contents of the next data
Dword as the 32-bit target base address.
To perform STREG by two different tasks, a kind of
arbitration with two semaphore signals is necessary.
Table 30 LDREG command format
Table 31 STREG command format
2004 Aug 25
1001
1010
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
D31 to D28
D31 to D28
Fig.6 Possible solution employing two semaphore signals to perform STREG commands with two tasks.
LDREG and STREG
reserved
reserved
D27 to D16
D27 to D16
handbook, halfpage
TASK0
SET SIG3
. . .
SET SIG3
CLR SIG3
JUMP IF SIG2 = 0 TO
STREG
ADDRESS
SET SIG3
. . .
Block_length
Block_length
D15 to D8
D15 to D8
35
The Block_length entry defines the number of data
Dwords to be processed by these commands. This
enables the access to multiple registers on following
addresses within a single RPS command. The value
specified must be at least one. If more than one Dword is
accessed the register address is incremented each cycle.
A value of zero is reserved and the command will be
interpreted as NOP.
The register address defines the target register address in
Dwords. If this address points to a non-existent register the
RPS_RE (read error) bit for the actual task will be set and
if enabled an interrupt will be generated. The command will
be ignored and the execution of RPS continues.
All reserved bits should be written as zeros and should be
ignored during read cycles.
TASK1
SET SIG2
. . .
. . .
CLR SIG2
WAIT ON SIG3
STREG
ADDRESS
SET SIG2
. . .
reserved
reserved
D7
D7
MHB048
register address
(register offset divided-by-4)
register address
(register offset divided-by-4)
Product specification
D6 to D0
D6 to D0
SAA7146A