SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 73

• Manufacturer Part Number: SAA7146AH/V4,557
• Description: IC VIDEO SPCI BRIDGE HP 160-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Bridger

Specifications of SAA7146AH/V4,557

• Package / Case: 160-QFP
• Applications: DTV
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1318; 935269343557; SAA7146AHBB

Philips Semiconductors
7.10.2.2
The timing reference signals (VS, HS, LLC and FID) are
taken from port A or port B. The BRS has to deliver pixel
with pixel clock of
there are no dropouts, a simple underflow handling is
performed by the DMA read module. If the PCI load is big
and a FIFO underflow occurs, the DMA read module uses
a grey value (10H for luminance, 80H for chrominance) or
the last pixel as a substitute. The FIFO control counts the
failed requests and removes the late values from the FIFO
hoping to catch up for lost time to the end of a line. At the
end of a line given by the external source the DMA tries to
read the data of the new line. This time is defined by the
horizontal offset (BXO) of the input acquisition, see Fig.25.
The PXQ can be used as KEY signal for the On Screen
Display (OSD) data to support panning, if the video
window has no full screen format.
2004 Aug 25
handbook, full pagewidth
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Direct mode
1
2
Fig.25 Reference signals for scaling window for direct and line memory mode.
LLC to the D1 port. To ensure that
BXO
(NumBytes/2)
ACTIVE VIDEO WINDOW
SCALING
WINDOW
result
line
73
scale ratio
7.10.2.3
The timing reference signals (VS, HS, LLC and FID) are
taken from port A or port B. The access time could be
extended by using a line memory at the D1 interface. If a
FIFO underflow occurs during the active processing, the
DMA read unit waits for the next valid data hoping to catch
up for the lost time during the horizontal blanking interval.
The timing is retriggered by the H-sync and V-sync.
Therefore it is possible, depending on the PCI load, that a
line or a part of a line is read multiple from the line memory.
The PXQ is used as a write enable signal (see Fig.26).
Line memory mode
HS
PXQ (only in direct mode)
frame
MGG265
field/
Product specification
SAA7146A