SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 108

• Manufacturer Part Number: SAA7146AH/V4,557
• Description: IC VIDEO SPCI BRIDGE HP 160-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Bridger

Specifications of SAA7146AH/V4,557

• Package / Case: 160-QFP
• Applications: DTV
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1318; 935269343557; SAA7146AHBB

Philips Semiconductors
7.16.4.2
Figure 39 illustrates the audio data path. An input
multiplexer selects serial data from one of four SD pins.
A1 can select SD0 and the common serial data pins SD1,
SD2 and SD3. A2 can select SD4 and the common serial
data pins SD1, SD2 and SD3. A serial-to-parallel converter
collects 8 bits to form a byte in a timeslot. At the end of the
time slot this byte can be stored into a Dword buffer, and/or
into the feedback buffer or can be thrown away. The first
byte that is latched, is placed into the first byte place of the
buffer, the second byte that is latched, is placed into the
second byte place, etc.
Big-endian and little-endian stuffing is supported. If bytes
are not latched into a certain buffer, the place pointer of the
corresponding buffer is not incremented. The write (fill)
pointer of the feedback buffer is reset to it’s initial position
2004 Aug 25
handbook, full pagewidth
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
Audio data path
INPUT BUFFER
AUDIO INPUT
24 DWORDS
SERIAL-TO-
PARALLEL
FIFO
8
serial data lines
Fig.39 Audio data flow control in A1 and A2.
SD0
SD4
feedback buffer
status/control
information
via PCI
SD1
108
32
SD2
with every start/restart of the super frame. Up to four bytes
of the input data stream can be placed in the intermediate
feedback buffer. They can be selected from the buffer to
provide data to the output.
The feedback buffer is also read and write accessible via
the PCI-bus. This allows reading of status information and
writing of control information at specific positions in the
audio frame. The write access is only possible when the
interface is inactive. The samples of the various real world
audio signal streams are byte or word interleaved in
system memory and PCI address space. It is the
responsibility of system/board designer and of
software/programmer to produce a reasonable sample
ordering, e.g. have a 16-bit sample on a word boundary
and not crossing a Dword boundary.
SD3
PARALLEL-
OUTPUT BUFFER
TO-SERIAL
AUDIO OUTPUT
24 DWORDS
8
FIFO
MGG277
Product specification
SAA7146A