SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 119

• Manufacturer Part Number: SAA7146AH/V4,557
• Description: IC VIDEO SPCI BRIDGE HP 160-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Bridger

Specifications of SAA7146AH/V4,557

• Package / Case: 160-QFP
• Applications: DTV
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1318; 935269343557; SAA7146AHBB

Philips Semiconductors
7.17.2.2
The protocol sequence for reading three bytes with
subaddress access is illustrated in Fig.42. The procedure
for this read operation is detailed below:
1. Address slave, write to IICTFR (see Fig.43):
2. Wait until BUSY = 0
3. Check ERR bit, if it is inactive the slave target is
4. Transfer data, write attribute information to IICTFR
5. Wait until BUSY = 0
6. Check ERR bit, if it is inactive IICTFR contains valid
2004 Aug 25
handbook, full pagewidth
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
BYTE2 [7:1] = DA, BYTE2 [0] = 0 (write),
ATTR2 = START
BYTE1 = subaddress, ATTR1 = CONT
BYTE0 [7:1] = DA, BYTE0 [0] = 1(read),
ATTR0 = START
successfully addressed
(see Fig.44):
BYTE2 = first received data byte, ATTR2 = CONT
BYTE1 = second received data byte, ATTR1 = CONT
BYTE0 = third received data byte, ATTR0 = STOP
data.
Example
Fig.42 Protocol sequence for reading three bytes with subaddress access.
S
S
restart for reading from slave
receive data
DA
DA
address device and transmit subaddress
D
W
R
119
A
A
A
Instead of checking the general error flag (ERR) after each
single 3-byte sequence, it is possible to check the ERR at
the end of the whole protocol sequence. During a bus
cycle, the BUSY bit is set HIGH. At the end of a bus cycle
an interrupt request is generated if enabled and BUSY is
cleared if no error occurs. Writing to the IICTRF should not
be done while the BUSY bit is active, otherwise the ERR
flag will be set HIGH. If no transfer errors occur during the
three transfer actions, the ERR bit will be set LOW. If an
error occurs the ERR bit will be set HIGH and the BUSY bit
stays HIGH. In this case the error and BUSY flags have to
be cleared before starting a new operation.
restart last byte and STOP
receive data
SA
D
D
NA
A
A
MGD696
P
Product specification
SAA7146A