SAA7146AH/V4,557 NXP Semiconductors, SAA7146AH/V4,557 Datasheet - Page 40

• Manufacturer Part Number: SAA7146AH/V4,557
• Description: IC VIDEO SPCI BRIDGE HP 160-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Bridger

Specifications of SAA7146AH/V4,557

• Package / Case: 160-QFP
• Applications: DTV
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1318; 935269343557; SAA7146AHBB

Philips Semiconductors
2004 Aug 25
110
OFFSET
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
(HEX)
RPS_TO0
UPLD
DEBI_S
DEBI_E
IIC_S
IIC_E
A2_in
A2_out
A1_in
A1_out
AFOU
V_PE
VFOU
NAME
21
20
19
18
17
16
15
14
13
12
11
10
9
BIT
R
R
R
R
R
R
R
R
R
R
R
R
R
TYPE
RPS time out error in Task 0: this bit is set when the RPS
Task 0 stays longer than expected in the WAIT state. This bit
is reset by starting a new RPS Task 0.
RPS in UPLOAD: this bit is active while RPS uploads the
working registers from the shadow RAM. The bit in the ISR is
set on the falling edge of this status bit.
DEBI Status: this bit stays set as long as DEBI is processing
or halted by an error. The bit in the ISR is set on the falling
edge of this status bit, which indicates a ‘DEBI Done’.
DEBI Event: this bit is set when one of the two DEBI event
flags (DEBI_EF or DEBI_TO) in the SSR is set. This bit is
reset when a new DEBI command starts. The reset value of
DEBI_TO is a logic 1.
I
transmitting data or halted by an error. The bit in the ISR is set
on the falling edge of this status bit, which indicates an
‘I
I
bits in the SSR is set. This bit is reset when a new I
transfer starts.
Audio input DMA2 protection: this bit is set when the audio
input DMA2 address generation exceeded an ‘address
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
Audio output DMA2 protection: this bit is set when the audio
output DMA2 address generation exceeded an ‘address
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
Audio input DMA1 protection: this bit is set when the audio
input DMA1 address generation exceeded an ‘address
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
Audio output DMA1 protection: this bit is set when the audio
output DMA1 address generation exceeded an ‘address
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
Audio FIFO Overflow/Underflow: this bit gets set when one
of the four audio FIFOs has an underflow or overflow.
Video address Protection Error: this bit is set when one of
the video DMAs 1 to 3 has an address protection error during
an active transmission.
Video FIFO Overflow/Underflow: this bit is set if any of the
video FIFOs 1, 2 or 3 has an overflow or underflow.
2
2
2
C-bus Status: this bit stays set as long as the I
C-bus Error: this bit gets set when one of the I
C-bus Done’.
40
DESCRIPTION
2
2
C-bus status
C-bus is
2
Product specification
C-bus
SAA7146A
RESET