mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 103

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 68:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Bank address
DQS, DQS#
Command
Address
CK#
CKE
A10
DQ 7
DM
CK
NOP 1
T0
WRITE – DM Operation
Notes:
Bank x
ACT
RA
T1
RA
t CK
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T11.
5.
6. Subsequent rising DQS signals must align to the clock within
7. DI n = data-in for column n; subsequent elements are applied in the programmed order.
8.
9.
NOP 1
times.
t
t
t
WR starts at the end of the data burst regardless of the data mask condition.
DSH is applicable during
DSS is applicable during
T2
t CH
t RCD
t CL
Bank x
WRITE 2
Col n
3
T3
AL = 1
NOP 1
T4
WL ± t DQSS (NOM)
t
t
DQSS (MAX) and is referenced from CK T7 or T8.
DQSS (MIN) and is referenced from CK T6 or T7.
WL = 2
NOP 1
103
T5
t WPRE
NOP 1
T6
DI
n
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t RAS
T6n
t DQSL t DQSH t WPST
512Mb: x4, x8, x16 DDR2 SDRAM
NOP 1
6
T7
T7n
NOP 1
T8
t
DQSS.
Transitioning Data
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NOP 1
T9
t WR 5
NOP 1
T10
Operations
One bank
All banks
Don’t Care
Bank x 4
T11
PRE
t RPA