mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 37

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
31. V
32. For each input signal—not the group collectively.
33. There are two sets of values listed for command/address:
34. This is applicable to READ cycles only. WRITE cycles generally require additional time
35. READs and WRITEs with auto precharge are allowed to be issued before
36. When a single-bank PRECHARGE command is issued,
37. This parameter has a two clock minimum requirement at any
38. The
39. The minimum internal READ-to-PRECHARGE time. This is the time from which the
40.
41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This
trip points.
signal, while
ing signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline val-
ues must be derated by adding the values from Tables 30 and 31 on pages 55–56. If the
DQS differential strobe feature is not enabled, then the DQS strobe is single-ended
and the baseline values must be derated using Table 32 on page 57. Single-ended DQS
data timing is referenced at DQS crossing V
ended DQS strobe are listed in Tables 33–35 on pages 57–58; listed values are already
derated for slew rate variations and converted from baseline values to V
on page 49.
t
at V
defined values, referenced from the logic trip points.
for a rising signal and V
for a rising signal and V
not equal to 1 V/ns, then the baseline values must be derated by adding the values
from Tables 28 and 29 on page 52.
due to
satisfied because
applies when the PRECHARGE (ALL) command is issued, regardless of the number of
banks open. For 8-bank devices (≥1Gb),
on page 28 lists
bank-ACTIVATE commands may be issued in a given
restriction still applies.
last 4-bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit
prefetch is when the READ command internally latches the READ so that data will
output CL later. This parameter is only applicable when
frequencies faster than 533 MHz when
tion AL + BL/2 applies.
automatically delay the internal PRECHARGE command until
satisfied.
t
rounded up to the next integer.
to the
t
4 + (4) clocks = 8 clocks.
equates to an average refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial
and automotive). To ensure all rows of all banks are properly refreshed, 8,192
REFRESH commands must be issued every 64ms (commercial) or 32ms (industrial
and automotive). The JEDEC
AUTOREFRESH commands is allowed.
IS
DAL = (nWR) + (
WR programmed to four clocks would have
IL
a
/V
,
REF
t
t
FAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four
IH
IH
t
t
WR parameter stored in the MR9–MR11 For example, -37E at
when the slew rate is 1 V/ns. The baseline values,
WR during auto precharge.
a
DDR2 overshoot/undershoot. See “AC Overshoot/Undershoot Specification”
values (for reference only) are equivalent to the baseline values of
t
DS
t
DH
b
t
RP [MIN] +
is referenced from V
t
b
RP/
t
RAS lockout feature is supported in DDR2 SDRAM.
is referenced from V
t
CK). Each of these terms, if not already an integer, should be
t
IL
IH
RAS (MIN) has to be satisfied as well. The DDR2 SDRAM will
(
(
AC
DC
37
t
) for a falling signal, while
CK [AVG] MIN).
) for a falling signal. If the command/address slew rate is
t
RFC MAX of 70,000ns is not required as bursting of
t
CK refers to the application clock period; nWR refers
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
AC Timing Operating Specifications
IL
(
t
RTP = 7.5ns. If
AC
t
RPA (MIN) =
(
DC
) for a rising signal and V
512Mb: x4, x8, x16 DDR2 SDRAM
REF
) for a rising signal and V
t
DAL = 4 + (15ns/3.75ns) clocks =
. The correct timing values for a single-
t
t
t
IS
FAW (MIN) period.
RP (MIN) +
t
t
t
RP timing applies.
IH
RTP/(2 ×
b
t
RTP/(2 ×
t
is referenced from V
t
b
IS
IS
is referenced from V
b
©2004 Micron Technology, Inc. All rights reserved.
a
,
,
t
t
t
IH
t
CK.
IH
RAS (MIN) has been
t
b
CK) ≤ 1, then equa-
a
t
, are the JEDEC-
t
CK (AVG) (Table 11
and
IL
CK) > 1, such as
t
(
CK = 3.75ns with
IH
AC
(
t
DC
REF
) for a falling
IS
t
RAS (MIN) is
t
t
b
RRD (MIN)
) for a fall-
RPA timing
,
t
values.
t
IS
IH
IH
b
,
b
(
IL
t
. The
AC
IH
(
DC
)
b
)