mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 116
mt47h64m8b6-5e-it
Manufacturer Part Number
mt47h64m8b6-5e-it
Description
512mb X4, X8, X16 Ddr2 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT47H64M8B6-5E-IT.pdf
(122 pages)
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Figure 82:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Bank address
Command
Address
DQS 3
DM 3
ODT
DQ 3
CK#
CKE
A10
CK
R
TT
Bank a
RESET Function
Col n
READ
T0
High-Z
High-Z
Notes:
NOP 2
T1
1. V
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS rep-
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the com-
5. Initialization timing is shown in Figure 38 on page 71.
resents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configu-
ration (x4, x8, x16).
pletion of the burst.
DD
, V
Bank b
Col n
READ
T2
DD
L, V
DD
Indicates A Break in
Time Scale
Q, V
NOP 2
T3
DO
TT
, and V
DO
NOP 2
T4
116
REF
System
DO
RESET
must be valid at all times.
t DELAY
Unknown
T5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
1
R
TT
On
High-Z
High-Z
Transitioning Data
t CL
©2004 Micron Technology, Inc. All rights reserved.
t CK
Start of normal 5
initialization
t CL
sequence
NOP 2
Ta0
T = 400ns (MIN)
4
t CKE (MIN)
Operations
All banks
Tb0
PRE
Don’t Care
High-Z
t RPA
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