mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 36

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
17. This parameter is not referenced to a specific voltage level but is specified when the
18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual
19. The DRAM output timing is aligned to the nominal or average clock. Most output
20. When DQS is used single-ended, the minimum limit is reduced by 100ps.
21.
22.
23. This is not a device limit. The device will operate with a negative value, but system
24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-
26. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
27. The data valid window is derived by achieving other specifications:
28.
29. This maximum value is derived from the referenced test load.
30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differen-
device output is no longer driving (
clock that latches it in. However, the input timing (in ns) references to the
when determining the required number of clocks. The following input parameters are
determined by taking the specified percentage times the
t
parameters must be derated by the actual jitter error when input clock jitter is
present; this will result in each parameter becoming larger. The following parameters
are required to be derated by subtracting
t
to be derated by subtracting
t
subtracting
t
while
require
ever, the total window will not degrade.
t
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (
t
performance could be degraded due to bus turnaround.
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on
driven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions HIGH (above V
V
x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
t
tion to the clock duty cycle and a practical data valid window can be derived.
t
t
offset and value of
valid data out window.
over
tial slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed:
t
baseline values of
baseline values,
IPW,
LZ
LZ
JIT
HZ and
LZ (MIN) will prevail over a
DQSQ, and
QH =
CH (ABS) MAX times
DH
IH
DQS
DQS
PER
[
DC
a
t
DQSCK (MAX) +
and
t
t
DIPW,
t
RPST (MAX), is derated by subtracting
]) prior to
HP -
(MIN). The parameter
(MIN),
(MAX),
t
ERR
t
LZ transitions occur in the same access time windows as valid data transi-
t
DS
t
t
t
JIT
5
QHS; the worst case
t
QH (
b
PER
DQSS,
,
t
t
LZ
LZ
PER
t
DH
t
derating can be observed to have offsets relative to the clock; how-
t
DS
DQSH (MIN).
DQ
t
DQ
t
QH =
t
DS
JIT
(MAX), while
b
b
t
. The
,
(MIN),
DQSH,
(MAX),
b
t
t
DTY
t
CK (ABS) MIN -
DH
,
RPST (MAX) condition.
t
t
DH
HP -
t
b
will provide a larger
DS
36
, are the JEDEC-defined values, referenced from the logic
b
t
t
t
t
t
AON (MIN); while the following parameters are required
DQSCK (MIN) +
ERR
DQSL,
AON (MAX). The parameter
a
at V
t
t
QHS). The data valid window derates in direct propor-
RPST (MIN) is derated by subtracting
,
IH
t
DH
t
t
REF
5
RPRE (MAX), is derated by subtracting
[
QH would be the lesser of
PER
DC
t
RPST) or beginning to drive (
a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DSS,
] MIN), then it must not transition LOW (below
when the slew rate is 2 V/ns, differentially. The
values (for reference only) are equivalent to the
(MIN):
t
AC Timing Operating Specifications
QHS. Minimizing the amount of
t
ERR
t
512Mb: x4, x8, x16 DDR2 SDRAM
DSH,
t
t
t
AC (MAX),
HZ) or begins driving (
t
JIT
5
RPRE (MAX) condition.
t
QH, which in turn will provide a larger
PER
t
DTY
WPST, and
(MAX):
t
(MIN). Output timings that
DQSS.
t
t
DQSCK (MAX),
CK (AVG) rather than
t
t
RPRE (MIN) is derated by
AC (MIN),
©2004 Micron Technology, Inc. All rights reserved.
t
t
CL (ABS) MAX or
WPRE.
t
HZ (MAX) will prevail
t
RPRE).
t
HP (
t
t
LZ).
JIT
t
DQSCK (MIN),
DTY
t
t
t
CH (AVG)
CK/2),
HZ (MAX),
t
CK (AVG)
(MAX),
t
CK:
t
DS
a
,