mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 89

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 54:
READ with Auto Precharge
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
READ-to-PRECHARGE – BL = 8
Notes:
DQS, DQS#
Command
Address
1. RL = 4 (AL = 1, CL = 3); BL = 8.
2.
3. Shown with nominal
If A10 is HIGH when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock
edge that is AL + (BL/2) cycles later than the READ with auto precharge command
provided
clock edge, the start point of the auto precharge operation will be delayed until
(MIN) is satisfied. If
the auto precharge operation will be delayed until
internal precharge is pushed out by
precharge happens (not at the next rising clock edge after this event).
When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE
command is AL + (
auto precharge to the next ACTIVATE command is AL + 2 clocks + (
term (
tion can also be used: AL + BL/2 - 2CK + (
precharge does not start earlier than two clocks after the last 4-bit prefetch.
READ with auto precharge command may be applied to one bank while another bank is
operational. This is referred to as concurrent auto precharge operation, as noted in
Table 41 on page 90. Examples of READ with precharge and READ with auto precharge
with applicable timing requirements are shown in Figure 55 on page 90 and Figure 56 on
page 91, respectively.
CK#
A10
DQ
CK
t
RTP ≥ 2 clocks.
t
RTP +
Bank a
READ
T0
t
RAS (MIN) and
AL = 1
t
RP)/
First 4-bit
prefetch
NOP
AL + BL/2 - 2CK + MAX ( t RTP/ t CK or 2CK)
T1
t
t
CK is always rounded up to the next integer. A general purpose equa-
RTP +
t
RTP (MIN) is not satisfied at this rising clock edge, the start point of
t
AC,
≥ t RAS (MIN)
t
t
NOP
RTP are satisfied. If
RP)/
T2
t
DQSCK, and
CL = 3
89
t
CK. When BL = 8, the minimum time from READ with
Second 4-bit
prefetch
≥ t RC (MIN)
NOP
T3
t
RTP,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
≥ t RTP (MIN)
t
t
RTP +
RP starts at the point where the internal
NOP
T4
512Mb: x4, x8, x16 DDR2 SDRAM
t
RAS (MIN) is not satisfied at this rising
DO
t
RP)/
t
RTP (MIN) is satisfied. When the
DO
Bank a
Valid
t
PRE
CK. In any event, the internal
T5
DO
Transitioning Data
DO
©2004 Micron Technology, Inc. All rights reserved.
NOP
T6
≥ t RP (MIN)
DO
t
RTP +
DO
NOP
T7
t
Operations
RP)/
DO
Don’t Care
t
DO
t
CK. The
RAS
Bank a
Valid
ACT
T8