mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 27

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 10:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Parameter/Condition
Self refresh current: CK and CK# at 0V;
CKE ≤ 0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
Operating bank interleave read current: All bank
interleaving reads, I
AL =
t
HIGH, CS# is HIGH between valid commands; Address
bus inputs are stable during deselects; Data bus
inputs are switching; See “I
page 25 for details
RC (I
t
DD
RCD (I
),
t
RRD =
DD
DDR2 I
Notes: 1–7 (page 27) apply to the entire table
) - 1 ×
t
RRD (I
Notes:
OUT
t
CK (I
DD
DD
= 0mA; BL = 4, CL = CL (I
Specifications and Conditions (continued)
DD
),
DD
1. I
2. Input slew rate is specified by AC parametric test conditions (Table 8 on page 25).
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.
5. Definitions for I
6. I
7. The following I
t
);
RCD =
7 Conditions” on
t
CK =
V
I
LOW
HIGH
Stable
Floating
Switching
Switching
devices when operated outside of the range 0°C ≤ T
T
T
DD
DD
DD
DD
C
C
DD
≤ 0°C
≥ 85°C
1, I
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
values must be met with all combinations of EMR bits 10 and 11.
t
= +1.8V ±0.1V, V
RCD (I
t
CK (I
DD
4R, and I
DD
DD
I
derated by 2 percent; and I
I
derated by 2 percent; I
derated by 30 percent; and I
increase by this amount if T
),
DD
DD
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals, not including masks or strobes
); CKE is
IN
IN
t
DD
RC =
2P and I
0, I
DD
≤ V
≥ V
DD
DD
s must be derated (I
DD
conditions:
),
7 require A12 in EMR1 to be enabled during testing.
IL
IH
DD
1, I
(
(
AC
AC
Q = +1.8V ±0.1V, V
DD
REF
DD
Symbol Configuration
) MAX
) MIN
I
3P (slow) must be derated by 4 percent; I
I
DD
I
2N, I
DD
DD
= V
27
6L
6
7
DD
DD
Q/2
2Q, I
Electrical Specifications – I
DD
x4, x8, x16
DD
2P must be derated by 20 percent; I
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
x4, x8
C
limits increase) on IT-option or on AT-option
3N, I
DD
x16
< 85°C and the 2X refresh option is still enabled)
DD
6 and I
6 must be derated by 80 percent (I
L = +1.8V ±0.1V, V
DD
512Mb: x4, x8, x16 DDR2 SDRAM
3P (fast), I
DD
7 must be derated by 7 percent
C
-25E/
≤ 85°C:
300
370
-25
7
3
DD
4R, I
-3E/-3
240
350
REF
7
3
©2004 Micron Technology, Inc. All rights reserved.
DD
= V
DD
4W, and I
4R and I
DD
-37E
225
340
7
3
DD
Q/2.
DD
C
3Pslow must be
Parameters
≤ +85°C.
DD
DD
DD
220
340
-5E
5W must be
5W must be
7
3
6 will
Units
mA
mA