mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 26

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 10:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge
current: I
=
t
valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All banks idle;
=
bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All banks idle;
t
control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All banks idle;
t
control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All banks open;
t
address bus inputs are stable; Data bus inputs are
floating
Active standby current: All banks open;
t
CKE is HIGH, CS# is HIGH between valid commands;
Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current: All banks open,
continuous burst writes; BL = 4, CL = CL (I
t
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
Operating burst read current: All banks open,
continuous burst reads, I
CL = CL (I
t
CS# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
Burst refresh current:
command at every
CS# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs
are switching
CK =
RCD =
CK =
CK =
CK =
CK=
CK =
RAS =
t
t
CK (I
CK (I
t
t
t
t
t
t
CK (I
CK (I
CK (I
CK (I
CK (I
CK (I
t
DD
DD
t
RAS MAX (I
RCD (I
DD
),
); CKE is LOW; Other control and address
OUT
DD
DD
DD
DD
DD
DD
t
), AL = 0;
RC =
),
),
DDR2 I
Notes: 1–7 (page 27) apply to the entire table
),
); CKE is HIGH, CS# is HIGH; Other
); CKE is HIGH, CS# is HIGH; Other
); CKE is LOW; Other control and
= 0mA; BL = 4, CL = CL (I
DD
t
t
t
RAS =
RAS =
RC =
); CKE is HIGH, CS# is HIGH between
t
RC (I
DD
t
RFC (I
t
t
),
CK =
DD
RC (I
t
t
DD
RAS MAX (I
RAS MAX (I
t
RP =
DD
t
OUT
),
CK =
DD
Specifications and Conditions
DD
t
4W
t
RAS =
CK (I
) interval; CKE is HIGH,
= 0mA; BL = 4,
),
t
RP (I
t
t
CK (I
RAS =
DD
t
DD
DD
DD
RAS MIN (I
),
DD
),
),
); CKE is HIGH,
t
DD
); refresh
t
RAS MIN (I
t
RP =
RP =
), AL = 0;
DD
), AL = 0;
t
t
RP (I
RP (I
DD
),
DD
DD
DD
t
t
CK
CK
);
);
);
Symbol Configuration
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
DD
DD
DD
4W
2Q
26
2N
3N
4R
2P
3P
0
1
5
Electrical Specifications – I
Slow PDN exit
Fast PDN exit
MR[12] = 0
MR[12] = 1
x4, x8, x16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x16
x16
x16
x16
x16
x16
x16
x16
512Mb: x4, x8, x16 DDR2 SDRAM
-25E/
100
135
115
165
195
295
205
275
230
230
-25
50
65
55
70
40
12
70
75
7
-3E/-3
120
105
150
170
250
180
235
180
185
90
45
55
50
60
35
12
65
70
7
©2004 Micron Technology, Inc. All rights reserved.
-37E
110
135
140
205
145
195
170
175
80
95
40
45
45
50
30
12
55
60
7
DD
Parameters
110
130
115
160
115
155
165
170
-5E
80
90
35
40
40
45
25
12
45
50
7
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA