mt47h64m8b6-5e-it Micron Semiconductor Products, mt47h64m8b6-5e-it Datasheet - Page 9

• Manufacturer Part Number: mt47h64m8b6-5e-it
• Description: 512mb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 4:
Figure 5:
PDF: 09005aef82f1e6e2/Source: 09005aef821aed36
512Mb_DDR2_x4x8x16_D2.fm - 512Mb DDR2: Rev. L; Core DDR2: Rev. C 4/08 EN
BA0, BA1
BA0, BA1
A0–A13,
A0–A12,
RAS#
CAS#
RAS#
CAS#
WE#
WE#
ODT
ODT
CKE
CK#
CKE
CK#
CS#
CS#
CK
CK
15
16
Address
register
Address
register
registers
registers
Control
Mode
Control
Mode
logic
64 Meg x 8 Functional Block Diagram
logic
32 Meg x 16 Functional Block Diagram
16
15
counter
counter
Refresh
Refresh
14
13
10
10
2
2
13
14
address
2
address
Row-
MUX
2
Row-
MUX
Column-
counter/
address
control
14
Column-
Bank
latch
counter/
logic
address
control
Bank
logic
latch
latch and
decoder
address
Bank 0
latch and
row-
decoder
address
Bank 0
Bank 1
row-
Bank 2
Bank 1
Bank 3
Bank 2
8
2
Bank 3
16,384
8
2
8,192
DM mask logic
13
(16,384 x 256 x 32)
I/O gating
(8,192 x 256 x 64)
Sense amplifiers
Sense amplifiers
Column
decoder
I/O gating
DM mask
8,192
decoder
Column
Memory
(x32)
16,384
Memory
Bank 0
256
Bank 0
logic
array
array
Bank 1
(x64)
Bank 1
256
Bank 2
Bank 2
Bank 3
Bank 3
Column 0, Column 1
Column 0, Column 1
internal
CK, CK#
32
Internal
CK, CK#
9
64
32
32
64
READ
latch
64
CK out
WRITE
drivers
FIFO
and
CK in
READ
latch
CK out
WRITE
drivers
CK in
Column 0, Column 1
FIFO
and
8
8
8
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Column 0, Column 1
Mask
Data
16
16
16
16
32
MUX
4
Mask
Data
generator
64
8
1
1
1
1
8
8
8
8
DQS
MUX
registers
generator
512Mb: x4, x8, x16 DDR2 SDRAM
Input
Data
2
2
2
2
16
16
16
16
DQS
registers
8
Input
Data
1
1
1
1
8
8
8
8
DQS, DQS#
16
2
2
2
2
16
16
16
16
1
8
UDQS, UDQS#
LDQS, LDQS#
CK, CK#
2
DRVRS
Functional Block Diagrams
DLL
16
4
2
CK, CK#
RCVRS
DRVRS
2
DLL
4
RCVRS
©2004 Micron Technology, Inc. All rights reserved.
sw1
sw1
sw1
sw1
sw1
sw1
sw1
sw1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
ODT control
ODT control
sw2
sw2
sw2
sw2
sw2
sw2
sw2
sw2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
R2
VssQ
VssQ
sw3
sw3
sw3
sw3
sw3
sw3
sw3
sw3
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
R3
V
V
DD
DD
Q
Q
DQ0–DQ15
UDQS, UDQS#
LDQS, LDQS#
UDM, LDM
RDQS
DM
DQ0–DQ7
RDQS#
DQS, DQS#