mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 104

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mt47h64m16hw-3

Manufacturer Part Number
mt47h64m16hw-3
Description
1gb X4, X8, X16 Ddr2 Sdram
Manufacturer
Micron Semiconductor Products
Datasheet

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Figure 65:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Bank address
DQS, DQS#
Command
Address
DQ 6
CK#
CKE
A10
DM
CK
Bank Write – Without Auto Precharge
NOP 1
T0
Notes:
Bank x
ACT
RA
T1
RA
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T9.
5. Subsequent rising DQS signals must align to the clock within
6. DI n = data-in for column n; subsequent elements are applied in the programmed order.
7.
8.
times.
t
t
t CK
DSH is applicable during
DSS is applicable during
NOP 1
t RCD
T2
t CH
t CL
WRITE 2
Bank x
Col n
3
T3
WL ± t DQSS (NOM)
t
t
DQSS (MAX) and is referenced from CK T6 or T7.
DQSS (MIN) and is referenced from CK T5 or T6.
WL = 2
NOP 1
104
T4
t WPRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RAS
NOP 1
T5
DI
n
T5n
t DQSL t DQSH t WPST
1Gb: x4, x8, x16 DDR2 SDRAM
NOP 1
5
T6
T6n
Transitioning Data
t
NOP 1
DQSS.
T7
©2003 Micron Technology, Inc. All rights reserved.
t WR
NOP 1
T8
Operations
One bank
All banks
Don’t Care
Bank x 4
PRE
T9
t RP

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