mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 76

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Mode Register (MR)
Burst Length
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after
15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configuration;
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are
The mode register is used to define the specific mode of operation of the DDR2 SDRAM.
This definition includes the selection of a burst length, burst type, CAS latency, oper-
ating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 38
on page 77. Contents of the mode register can be altered by reexecuting the LOAD
MODE (LM) command. If the user chooses to modify only a subset of the MR variables,
all variables must be programmed when the command is issued.
The MR is programmed via the LM command and will retain the stored information
until it is programmed again or until the device loses power (except for bit M8, which is
self-clearing). Reprogramming the mode register will not alter the contents of the
memory array, provided it is performed correctly.
The LM command can only be issued (or reissued) when all banks are in the precharged
state (idle state) and no bursts are in progress. The controller must wait the specified
time
Violating either of these requirements will result in an unspecified operation.
Burst length is defined by bits M0–M2, as shown in Figure 38 on page 77. Read and write
accesses to the DDR2 SDRAM are burst-oriented, with the burst length being program-
mable to either four or eight. The burst length determines the maximum number of
column locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most
significant column address bit for a given configuration). The remaining (least signifi-
cant) address bit(s) is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
the DLL RESET at Tf0.
DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate
configuration (x4, x8, x16); DQ represents DQ0–DQ3 for x4, DQ–DQ7 for x8 and DQ0–DQ15
for x16.
required to be decoded).
t
MRD before initiating any subsequent operations such as an ACTIVATE command.
76
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Operations