mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 66

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Commands
Truth Tables
Table 38:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Function
LOAD MODE
REFRESH
SELF REFRESH entry
SELF REFRESH exit
Single bank PRECHARGE
All banks PRECHARGE
Bank activate
WRITE
WRITE with auto
precharge
READ
READ with auto
precharge
NO OPERATION
Device DESELECT
Power-down entry
Power-down exit
Truth Table – DDR2 Commands
Notes: 1–3 apply to the entire table
Notes:
Previous
The following tables provide a quick reference of available DDR2 SDRAM commands,
including CKE power-down modes and bank-to-bank commands.
Cycle
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the
2. The state of ODT does not affect the states described in this table. The ODT function is not
3. “X” means “H or L” (but a defined logic level) for valid I
4. BA2 is only applicable for densities >1Gb.
5. An is the most significant address bit for a given density and configuration. Some larger
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 50 on
9. The power-down mode does not perform any REFRESH operations. The duration of power-
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
rising edge of the clock.
available during self refresh. See “ODT Timing” on page 120 for details.
address bits may be “Don’t Care” during column addressing, depending on density and con-
figuration.
MODE command selects which mode register is programmed.
page 90 and Figure 62 on page 101 for other restrictions and details.
down is limited by the refresh requirements outlined in the AC parametric section.
CKE
Current
Cycle
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
CS#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS# WE#
X
H
H
H
H
H
H
X
X
H
X
H
L
L
L
L
L
L
66
H
H
H
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
X
H
H
H
H
H
X
X
H
X
H
L
L
L
L
L
BA2–
BA0
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
1Gb: x4, x8, x16 DDR2 SDRAM
An–A11 A10 A9–A0
Column
Column
Column
Column
address
address
address
address
DD
X
X
X
X
X
X
X
X
X
measurements.
Row address
OP code
©2003 Micron Technology, Inc. All rights reserved.
H
H
H
X
X
X
X
X
X
X
L
L
L
Column
Column
Column
Column
address
address
address
address
X
X
X
X
X
X
X
X
X
Commands
4, 5, 6, 8
4, 5, 6, 8
4, 5, 6, 8
4, 5, 6, 8
Notes
4, 6
4, 7
6
4
9
9