mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 53

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 29:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Parameter
Input setup timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM,
UDM, LDM, and CKE
Input hold timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT, DM,
UDM, LDM, and CKE
Input timing measurement reference level (single-ended)
DQS for x4, x8; UDQS, LDQS for x16
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,
RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16
AC Input Test Conditions
Notes:
1. All voltages referenced to V
2. Input waveform setup timing (
3. See “Input Slew Rate Derating” on page 54.
4. The slew rate for single-ended inputs is measured from DC level to AC level, V
5. Input waveform hold (
6. Input waveform setup timing (
7. Input waveform setup timing (
8. Input waveform timing is referenced to the crossing point level (V
9. The slew rate for differentially ended inputs is measured from twice the DC level to twice
V
test, as shown in Figure 33 on page 64.
V
to V
Figures 26, 28, 30, and 32.
level for a rising signal and V
shown in Figure 33 on page 64.
referenced from the crossing of DQS, UDQS, or LDQS through the V
device under test, as shown in Figure 35 on page 65.
enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/LDQS#, as
shown in Figure 34 on page 64.
(V
the complementary input signal, as shown in Figure 36 on page 65.
the AC level: 2 × V
falling edge. For example, the CK/CK# would be –250mV to +500mV for CK rising edge and
would be +250mV to –500mV for CK falling edge.
IH
IH
TR
(
(
AC
AC
REF
and V
) level for a rising signal and V
) on the rising edge and V
, the valid intersection is where the “tangent” line intersects V
CP
) applied to the device under test, where V
IL
(
DC
t
) to 2 × V
IH
b
) timing is referenced from the input signal crossing at the V
SS
53
IH
.
t
(
t
t
Symbol
IS
DS) and hold timing (
DS) and hold timing (
IH
DC
V
IL
REF
b
(
(
V
V
) for a falling signal applied to the device under test, as
AC
V
) is referenced from the input signal crossing at the
AC
RH
RD
RS
AC Overshoot/Undershoot Specification
(
) on the rising edge and 2 × V
DC
IL
) to V
(
AC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
)
) for a falling signal applied to the device under
IH
(
DC
V
) on the falling edge. For signals referenced
DD
Q × 0.49 V
Min
1Gb: x4, x8, x16 DDR2 SDRAM
t
t
See Note 2
See Note 5
DH) for single-ended data strobe is
DH) when differential data strobe is
V
TR
IX
(
is the true input signal and V
AC
)
DD
Max
Q × 0.51
©2003 Micron Technology, Inc. All rights reserved.
IL
IX
(
AC
REF
) of two input signals
REF
) to 2 × V
level applied to the
, as shown in
Units
V
V
IL
IH
(
DC
(
DC
) to
) on the
Notes
1, 2, 3,
1, 3, 4,
1, 3, 4,
1, 3, 7,
8, 9
IL
4
5
6
CP
(
DC
is
)