mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 109

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

SELF REFRESH
Figure 70:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
DQS#, DQS
Command
Address
ODT 6
CKE 1
CK#
CK 1
DM
DQ
Self Refresh
mode (synchronous)
Enter self refresh
t AOFD/ t AOFPD 6
NOP
T0
Notes:
t CH
t RP 8
t CL
10. Upon exiting SELF REFRESH, ODT must remain LOW until
The SELF REFRESH command is initiated with CKE is LOW. The differential clock should
remain stable and meet
mode. The procedure for exiting self refresh requires a sequence of commands. First, the
differential clock must be stable and meet
going back to HIGH. Once CKE is HIGH (
registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for
t
NOP or DESELECT commands for 200 clock cycles before applying any other command.
1. Clock must be stable and meeting
2. Self refresh exit is asynchronous; however,
3. CKE must stay HIGH until
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0, which
5.
6. ODT must be disabled and R
7.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered,
XSNR. A simple algorithm for meeting both refresh and DLL requirements is to apply
REF
T1
refresh mode and at least 1 ×
clock edge where CKE HIGH satisfies
go back LOW after
allows any nonREAD command.
t
self refresh at state T1.
t
refresh.
XSNR is required before any nonREAD command can be applied.
XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
t CK 1
T2
t CKE (MIN) 9
t
XSNR is satisfied.
mode (asynchronous)
Ta0
t
Exit self refresh
CKE specifications at least 1 ×
t
XSRD is met; however, if self refresh is being reentered, CKE may
t CK 1
TT
109
t
off (
CK prior to exiting self refresh mode.
Ta1
t
t
CK specifications at least 1 ×
AOFD and
t
t
CKE (MIN) must be satisfied prior to exiting self
ISXR.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t ISXR 2
t
CKE [MIN] has been satisfied with three clock
NOP 4
t
CK specifications at least 1 ×
t
XSNR and
Ta2
t
AOFPD have been satisfied) prior to entering
t CKE 3
1Gb: x4, x8, x16 DDR2 SDRAM
t XSNR 2, 5, 10
t
XSRD timing starts at the first rising
NOP 4
Tb0
t
CK after entering self refresh
Indicates A Break in
Time Scale
t
XSRD is satisfied.
t XSRD 2, 7
©2003 Micron Technology, Inc. All rights reserved.
t
CK after entering self
Valid 5
Valid
Tc0
t
CK prior to CKE
Operations
Don’t Care
Valid 7
Valid 5
Td0
t IH
t IH