mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 16

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 4:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1Gb_DDR2_x4x8x16_D2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
T2, T8, T3, T7,
U2, U8, U3,
R8, R3, R7,
R2, U7, V2
Number
P2, P3, P1
x16 Ball
M8, N8
J3, E3
N2
P8
–
92-Ball – x4, x8, x16 Descriptions
R8, R3, R7, T2,
T8, T3, T7, U2,
x4, x8 Ball
U8, U3, R2,
U7, V2, V8
Number
P2, P3, P1
M8, N8
N2
P8
J3
–
LDM, UDM,
BA0–BA2
A10–A12
A11–A13
Symbol
A8–A10,
CK, CK#
A0–A2,
A3–A6,
A7–A9,
A0–A3,
A4–A7,
(DM)
CKE
CS#
Input
Input
Input
Input
Input
Input
Input
Type
Description
Address inputs: Provide the row address for ACTIVATE
commands, and the column address and auto precharge bit (A10)
for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0–BA2) or all
banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command.
Address inputs: Provide the row address for ACTIVATE
commands, and the column address and auto precharge bit (A10)
for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0–BA2) or all
banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command.
Bank address inputs: BA0–BA2 define to which bank an
ACTIVATE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA2 define which mode register including MR, EMR,
EMR(2), and EMR(3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQ and DQS/
DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the
DDR2 SDRAM configuration and operating mode. CKE LOW
provides precharge power-down and SELF REFRESH operation (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry, power-down exit, output
disable, and self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled
during power-down. Input buffers (excluding CKE) are disabled
during self refresh. CKE is an SSTL_18 input but will detect a
LVCMOS LOW level after V
After V
initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper SELF REFRESH operation,
V
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS#
is registered HIGH. CS# provides for external bank selection on
systems with multiple ranks. CS# is considered part of the
command code.
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM
balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is
DM for upper byte DQ8–DQ15.
REF
16
must be maintained.
REF
has become stable during the power-on and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
1Gb: x4, x8, x16 DDR2 SDRAM
DD
is applied during first power-up.
©2004 Micron Technology, Inc. All rights reserved.