mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 38

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Notes
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
10. MIN (
11.
12. The period jitter (
13. The half-period jitter (
14. The cycle-to-cycle jitter (
15. The cumulative jitter error (
16. JEDEC specifies using
1. All voltages are referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load (see Figure 17 on page 46).
4. AC timing and I
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that
6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
7. Operating frequency is only allowed to change during self refresh mode (see Figure 80
8. The clock’s
9. Spread spectrum is not included in the jitter specification values. However, the input
at nominal reference/supply voltage levels, but the related specifications and the
operation of the device are warranted for the full voltage range specified. ODT is dis-
abled for all measurements that are not ODT-specific.
ment, and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The slew rate for the input signals used to test the
device is 1.0 V/ns for signals in the range between V
other than 1.0 V/ns may require the timing parameters to be derated as specified.
is, the receiver will effectively switch as a result of the signal crossing the AC input
level and will remain in that state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
on page 117), precharge power-down mode, or system reset condition (see "Reset" on
page 118). SSC allows for small deviations in operating frequency, provided the SSC
guidelines are satisfied.
t
allowed clock jitter). Input clock jitter is allowed provided it does not exceed values
specified. Also, the jitter must be of a random Gaussian distribution in nature.
clock can accommodate spread spectrum at a sweep rate in the range 20–60 KHz with
an additional one percent
clock rate below
HIGH time driven to the device. The clock’s half period must also be of a Gaussian dis-
tribution;
or without duty cycle jitter.
secutive CK falling edges.
t
inputs; thus,
age or nominal clock allowed in either the positive or negative direction. JEDEC spec-
ifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter
values should be 20 percent less those than noted in the table (DLL locked).
pulse of clock; however, the two cumulatively can not exceed
cycle to the next. JEDEC specifies tighter jitter numbers during DLL locking time.
During DLL lock time, the jitter values should be 20 percent less than those noted in
the table (DLL locked).
amount of clock time allowed to consecutively accumulate away from the average
clock over any number of clock cycles.
notes 19 and 48). Micron requires less derating by allowing
CK (AVG) MIN is the smallest clock rate allowed (except for a deviation due to
HP (MIN) is the lesser of
t
CL,
t
t
CH (AVG) and
CH) refers to the smaller of the actual clock LOW time and the actual clock
t
CK (AVG) is the average clock over any 200 consecutive clocks and
t
HP (MIN) ≥ the lesser of
DD
t
CK
t
JIT
tests may use a V
(AVG) MIN or above
DD
PER
t
t
JIT
ERR
, and electrical AC and DC characteristics may be conducted
) is the maximum deviation in the clock period from the aver-
t
t
t
JIT
CL (AVG) must be met with or without clock jitter and with
DTY
CL and
t
38
CK (AVG); however, the spread spectrum may not use a
6–10
t
t
CH (AVG) and
ERR
CC
) applies to either the high pulse of clock or the low
SS
) is the amount the clock period can deviate from one
PER
.
n
t
PER
when derating clock-related output timing (see
CH actually applied to the device CK and CK#
IL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
), where n is 2, 3, 4, 5, 6–10, or 11–50 is the
-to-V
t
CL (ABS) MIN and
AC Timing Operating Specifications
t
CK
t
IH
CL (AVG) are the average of any 200 con-
(AVG)
swing of up to 1.0V in the test environ-
1Gb: x4, x8, x16 DDR2 SDRAM
MAX.
IL
(
AC
) and V
t
CH (ABS) MIN.
t
©2003 Micron Technology, Inc. All rights reserved.
ERR
t
JIT
IH
5
PER
PER
(
AC
to be used.
.
). Slew rates