mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 72

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

REFRESH
SELF REFRESH
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
not violate any other timing parameters. After a bank has been precharged, it is in the
idle state and must be activated prior to any READ or WRITE commands being issued to
that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle
state) or if the previously open row is already in the process of precharging. However, the
precharge period will be determined by the last PRECHARGE command issued to the
bank.
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to
CAS#-before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing a
REFRESH command. This command is nonpersistent, so it must be issued each time a
refresh is required. The addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during a REFRESH command.
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if
the rest of the system is powered down. When in the self refresh mode, the DDR2
SDRAM retains data without external clocking. All power supply inputs (including V
must be maintained at valid levels upon entry/exit and during SELF REFRESH opera-
tion.
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering self refresh and is automatically
enabled upon exiting self refresh.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Commands
REF
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