mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 112

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 45:
PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
Current State
Bank(s) active
All banks idle
Power-down
Self refresh
Truth Table – CKE
Notes 1–4 apply to the entire table
Notes:
Previous
(n - 1)
Cycle
H
H
H
H
L
L
L
L
10. Valid commands for self refresh exit are NOP and DESELECT only.
11. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD
12. Minimum CKE HIGH time is
13. Self refresh mode can only be entered from the all banks idle state.
14. Must be a legal command, as defined in Table 38 on page 66.
1. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the pre-
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and action (n) is a result of com-
4. The state of ODT does not affect the states described in this table. The ODT function is not
5. Power-down modes do not perform any REFRESH operations. The duration of power-down
6. “X” means “Don’t Care” (including floating around V
7. All states and sequences not shown are illegal or reserved unless explicitly described else-
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occur-
vious clock edge.
mand (n).
available during self refresh (see "ODT Timing" on page 120 for more details and specific
restrictions).
mode is therefore limited by the refresh requirements.
However, ODT must be driven HIGH or LOW in power-down if the ODT function is enabled
via EMR.
where in this document.
ring during the
is satisfied.
MODE operations, or PRECHARGE operations are in progress. See “SELF REFRESH” on
page 109 and “SELF REFRESH” on page 72 for a list of detailed restrictions.
requires a minimum of 3 clock cycles of registration.
CKE
Cycle (n)
Current
H
H
H
L
L
L
L
L
t
XSNR period. READ commands may be issued only after
Command (n) CS#,
RAS#, CAS#, WE#
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
REFRESH
t
112
CKE = 3 ×
X
X
Shown in Table 38 on page 66
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CK. Minimum CKE LOW time is
Precharge power-down entry
Active power-down entry
Maintain power-down
1Gb: x4, x8, x16 DDR2 SDRAM
Maintain self refresh
Self refresh entry
Power-down exit
Self refresh exit
REF
Action (n)
) in self refresh and power-down.
©2003 Micron Technology, Inc. All rights reserved.
t
CKE = 3 ×
t
XSRD (200 clocks)
Operations
7, 8, 11, 12
10, 12, 13
7, 9, 10
7, 8, 11
Notes
t
5, 6
7, 8
CK. This
14
6