mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 74

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Command
Address
DQS
DM
DQ
V
V
V
ODT
V
DD
CK#
CKE
V
DD
R
TT
CK
REF
15
16
15
15
DD
TT
Q
1
L
low level 2
LVCMOS
High-Z
High-Z
High-Z
t
VTD 1
T0
t CL
V
clock (CK, CK#)
T = 200µs (MIN) 3
Power-up:
low level
SSTL_18
DD
Notes:
t CK
and stable
t CL
2
1. Applying power; if CKE is maintained below 0.2 × V
V
must be less than V
the device; however,
or B) must be met to obtain a stable supply state (stable supply defined as V
their minimum and maximum values as stated in Table 14 on page 41):
NOP 3
REF
Ta0
T = 400ns (MIN) 4
must be valid and a low level must be applied to the ODT ball (all other inputs may be undefined; I/Os and outputs
A10 = 1
Tb0
PRE
t RPA
Figure 37: DDR2 Power-Up and Initialization
EMR(2)
DD
LM 5
Code
Tc0
t
Q during voltage ramp time to avoid DDR2 SDRAM device latch-up). V
VTD should be ≥0 to avoid device latch-up. At least one of the following two sets of conditions (A
t MRD
EMR(3)
Code
LM 6
Td0
t MRD
Code
LM 7
EMR
Te0
t MRD
DLL RESET
MR with
Code
LM 8
Tf0
DD
Q, outputs remain disabled. To guarantee R
t MRD
A10 = 1
PRE 9
Tg0
t RPA
200 cycles of CK are required before a READ command can be issued
REF 10
Th0
t RFC
See note 10
REF 10
Ti0
DD
, V
t RFC
DD
MR without
DLL RESET
LM 11
Code
L, V
Tj0
DD
t MRD
Q, V
OCD default
EMR with
TT
LM 12
Code
Tk0
Indicates A Break in
Time Scale
REF
TT
is not applied directly to
, and V
(ODT resistance) is off,
t MRD
EMR with
OCD exit
LM 13
Code
Tl0
TT
are between
t MRD
operation
Normal
Don’t care
Valid 14
Valid
Tm0