mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 8

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Figure 4:
Figure 5:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1Gb_DDR2_x4x8x16_D2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
BA0-BA2
BA0–BA2
A0-A14,
A0–A13,
RAS#
CAS#
RAS#
CAS#
ODT
WE#
WE#
CKE
CK#
ODT
CKE
CK#
CS#
CS#
CK
CK
18
18
REGISTER
ADDRESS
REGISTER
ADDRESS
REGISTERS
REGISTERS
MODE
MODE
CONTROL
CONTROL
128 Meg x 8 Functional Block Diagram
64 Meg x 16 Functional Block Diagram
LOGIC
LOGIC
18
18
COUNTER
COUNTER
REFRESH
REFRESH
15
14
10
10
3
3
14
ADDRESS
ADDRESS
ROW-
2
ROW-
MUX
2
MUX
CONTROL
CONTROL
15
COUNTER/
13
COUNTER/
LOGIC
COLUMN-
COLUMN-
BANK
ADDRESS
BANK
LOGIC
ADDRESS
LATCH
LATCH
DECODER
ADDRESS
DECODER
ADDRESS
BANK 0
BANK 0
LATCH
LATCH
ROW-
ROW-
BANK 1
BANK 1
&
&
BANK 2
BANK 2
BANK 3
BANK 3
BANK 4
BANK 4
8
2
8
2
BANK 5
32,768
16,324
BANK 5
BANK 6
BANK 6
BANK 7
BANK 7
DM MASK LOGIC
DM MASK LOGIC
(32,768 x 256 x 32)
(16,324 x 256 x 64)
SENSE AMPLIFIERS
I/O GATING
I/O GATING
SENSE AMPLIFIERS
DECODER
DECODER
COLUMN
COLUMN
16,384
MEMORY
MEMORY
8,192
(x32)
(x64)
BANK 0
256
BANK 0
ARRAY
ARRAY
256
BANK 1
BANK 1
BANK 2
BANK 2
BANK 3
BANK 3
BANK 4
BANK 4
BANK 5
BANK 5
BANK 6
BANK 6
BANK 7
BANK 7
8
COL0,COL1
COL0,COL1
CK,CK#
CK,CK#
32
64
32
64
32
64
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LATCH
LATCH
READ
READ
CK OUT
CK OUT
DRIVERS
DRIVERS
WRITE
WRITE
CK IN
CK IN
FIFO
FIFO
&
&
8
8
16
16
16
16
8
8
MASK
MASK
DATA
DATA
COL0,COL1
COL0,COL1
4
32
8
64
MUX
MUX
GENERATOR
GENERATOR
1Gb: x4, x8, x16 DDR2 SDRAM
2
2
2
8
8
8
8
2
2
2
16
16
16
16
REGISTERS
2
REGISTERS
2
DQS
DQS
INPUT
INPUT
DATA
DATA
16
Functional Block Diagrams
8
UDQS, UDQS#
LDQS, LDQS#
UDQS, UDQS#
LDQS, LDQS#
2
2
2
16
16
16
16
2
2
2
2
8
8
8
8
2
4
16
2
CK,CK#
CK,CK#
8
2
2
DRVRS
DRVRS
4
2
DLL
DLL
RCVRS
RCVRS
©2004 Micron Technology, Inc. All rights reserved.
sw1 sw2
sw1 sw2
sw1 sw2
sw1 sw2
R1
R1
R1
R1
R1
R1
sw1 sw2
sw1 sw2
sw1 sw2
sw1 sw2
R1
R1
R1
R1
R1
R1
ODT CONTROL
ODT CONTROL
R2
R2
R2
R2
R2
R2
VssQ
R2
R2
R2
R2
R2
R2
VssQ
sw3
sw3
sw3
sw3
sw3
R3
R3
R3
R3
R3
R3
sw3
sw3
sw3
R3
R3
R3
R3
R3
R3
V
V
DD
DD
Q
Q
UDQS, UDQS#
LDQS, LDQS#
DQ0–DQ15
DQS, DQS#
UDM, LDM
DQ0–DQ7
RDQS#
RDQS
DM