mt47h64m16hw-3 Micron Semiconductor Products, mt47h64m16hw-3 Datasheet - Page 75

• Manufacturer Part Number: mt47h64m16hw-3
• Description: 1gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

PDF: 09005aef8117c187/Source: 09005aef821aed36
DDR2_x4x8x16_Core2.fm - 1Gb DDR2: Rev. N; Core DDR2: Rev. C 4/08 EN
10. Issue two or more REFRESH commands.
11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9
2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device
3. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT
4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.
5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW to
6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH
7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command,
8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required
9. Issue PRECHARGE ALL command.
A. Single power source: The V
power-up prior to V
levels. Once CKE transitions to a high level, it must stay HIGH for the duration of the initial-
ization sequence.
commands, then take CKE HIGH.
BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self
refresh rate; remaining EMR(2) bits must be “0” (see "Extended Mode Register 2 (EMR2)"
on page 84 for all EMR(2) requirements).
to BA0 and BA1; remaining EMR(3) bits must be “0.” See “Extended Mode Register 3 (EMR
3)” on page 85 for all EMR(3) requirements.
provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or
“1;” Micron recommends setting them to “0;” remaining EMR bits must be “0.” See
“Extended Mode Register (EMR)” on page 80 for all EMR requirements.
to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0;
CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be “0.” See
“Mode Register (MR)” on page 76 for all MR requirements.
(that is, to program operating parameters without resetting the DLL). To access the MR, set
BA0 and BA1 LOW; remaining MR bits must be set to desired settings. See “Mode Register
(MR)” on page 76 for all MR requirements.
E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0 LOW
and BA1 HIGH (see "Extended Mode Register (EMR)" on page 80 for all EMR requirements.
to “0,” and then setting all other desired parameters. To access the extended mode regis-
ters, EMR, set BA0 LOW and BA1 HIGH for all EMR requirements.
B. Multiple power sources: V
longer than 200ms; during the V
age ramping is complete (when V
tions apply.
ramping, for both AC and DC levels, until supply voltage ramping completes (V
crosses V
fications apply.
• V
• V
• V
• V
• Apply V
• Apply V
• V
• Apply V
ply ramp time
time must be ≤200ms from when V
when V
V
supply ramp time; V
V
DD
TT
DD
TT
REF
DD
REF
DD
(MIN) is achieved must be no greater than 500ms
, V
is limited to 0.95V MAX
Q ≥ V
is ramping, current can be supplied from V
tracks V
must track V
DD
[MIN]). Once supply voltage ramping is complete, Table 14 on page 41 speci-
DD
DD
DD
TT
L, and V
REF
; the V
(MIN) is achieved to when V
Q before or at the same time as V
and V
REF
DD
at all times
being stable. After state T0, CKE is required to have SSTL_18 input
Q/2; V
TT
DD
DD
DD
voltage ramp time from when V
L before or at the same time as V
Q are driven from a single power converter output
Q/2; V
DD
75
DD
REF
DD
Q ≥ V
≥ V
must be within ±0.3V with respect to V
voltage ramp from 300mV to V
REF
DD
DD
REF
DD
must be within ±0.3V with respect to V
L ≥ V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
voltage ramp, |V
Q crosses V
must be met at all times
DD
DD
Q must be maintained during supply voltage
ramps from 300mV to V
DD
Q (MIN) is achieved must be ≤500ms; while
1Gb: x4, x8, x16 DDR2 SDRAM
DD
TT
[MIN]), Table 14 on page 41 specifica-
; the V
DD
DD
- V
through the device to V
DD
DD
DD
DD
Q (MIN) is achieved to when
Q; V
Q voltage ramp time from
©2003 Micron Technology, Inc. All rights reserved.
Q| ≤ 0.3V. Once supply volt-
DD
DD
(MIN) must take no
/V
DD
DD
DD
(MIN)
Q/2 during sup-
L voltage ramp
Operations
DD
Q/2 during
DD
DD
Q
Q