mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 173

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mc68hc912dg128

Manufacturer Part Number
mc68hc912dg128
Description
M68hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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11.6.14 PLL Register Descriptions
SYNR — Synthesizer Register
MC68HC912DG128 — Rev 3.0
MOTOROLA
Pseudo-STOP exit in Limp Home
Pseudo-STOP exit
in Limp Home mode without
Pseudo-STOP exit without Limp
Pseudo-STOP exit without Limp
Pseudo-STOP exit without Limp
RESET:
mode with Delay
Delay (Fast Stop Recovery)
Home mode, clock monitor
enabled
Home mode, clock monitor
disabled, with Delay
Home mode, clock monitor
disabled, without Delay
Bit 7
Mode
0
0
Table 11-2. Summary of Pseudo STOP Mode Exit Conditions
6
0
0
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
Freescale Semiconductor, Inc.
For More Information On This Product,
SYN5
NOLHM=0
CME=X
DLY=1
NOLHM=0
CME=X
DLY=0
NOLHM=1
CME=1
DLY=X
NOLHM=1
CME=0
DLY=1
NOLHM=1
CME=0
DLY=0
Conditions
5
0
Go to: www.freescale.com
SYN4
Clock Functions
4
0
CPU exits stop in limp home mode and oscillator running. If
This mode is not recommended as it is possible that the
When a STOP instruction is executed the MCU resets via
Oscillator starts operation following 4096 XCLK cycles
This mode is only recommended for use with an external
the oscillator fails during pseudo-STOP and then recovers
there is a possibility of code runaway as the clock monitor
circuit can be misled by EXTALi clock into reporting a
good signal before it has fully stabilised
initial VCO clock frequency may be high enough to cause
code runaway.
the clock monitor reset vector.
(actual controlled by SLOW mode divider).
clock source.
SYN3
3
0
Limp-Home and Fast STOP Recovery modes
SYN2
2
0
Summary
SYN1
1
0
SYN0
Bit 0
0
Clock Functions
Technical Data
$0038
173

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