mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 282

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Inter-IC Bus
Technical Data
282
Freescale Semiconductor, Inc.
The number of clocks from the falling edge of SCL to the first tap
(Tap[1]) is defined by the values shown in the scl2tap column of
15-1, all subsequent tap points are separated by 2
the tap2tap column in
the SCL period and the SDA Tap is used to determine the delay from
the falling edge of SCL to SDA changing, the SDA hold time.
The serial bit clock frequency is equal to the CPU clock frequency
divided by the divider shown in
generate the divider values from the IBFD bits is:
The SDA hold delay is equal to the CPU clock period multiplied by the
SDA Hold value shown in
the SDA Hold value from the IBFD bits is:
IBC2-0
(bin)
000
001
010
100
101
011
110
111
For More Information On This Product,
SCL Divider = 2 x ( scl2tap + [ ( SCL_Tap -1 ) x tap2tap ] + 2 )
SDA Hold = scl2tap + [ ( SDA_Tap - 1 ) x tap2tap ] + 3
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SCL Tap
(clocks)
Table 15-1. IIC Tap and Prescale Values
10
12
15
5
6
7
8
9
Inter-IC Bus
SDA Tap
(clocks)
Table
1
1
2
2
3
3
4
4
Figure
15-1. The SCL Tap is used to generated
Table
15-2. The equation used to generate
15-2. The equation used to
IBC5-3
(bin)
000
001
010
011
100
101
110
111
MC68HC912DG128 — Rev 3.0
(clocks)
scl2tap
IBC5-3
126
14
30
62
4
4
6
6
as shown in
MOTOROLA
(clocks)
tap2tap
128
16
32
64
1
2
4
8
Table