mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 267

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

14.5.5 Register Descriptions
SP0CR1 — SPI Control Register 1
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
SPIE
Bit 7
0
SPE
6
0
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to
Read or write anytime.
SPIE — SPI Interrupt Enable
SPE — SPI System Enable
SWOM — Port S Wired-OR Mode
MSTR — SPI Master/Slave Mode Select
Freescale Semiconductor, Inc.
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
When MODF is set, MSTR always reads zero. SP0CR1 must be
written as part of a mode fault recovery sequence.
For More Information On This Product,
0 = SPI interrupts are inhibited
1 = Hardware interrupt sequence is requested each time the SPIF
0 = SPI internal hardware is initialized and SPI system is in a low-
1 = PS[4:7] are dedicated to the SPI function
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
0 = Slave mode
1 = Master mode
SWOM
5
0
or MODF status flag is set
power disabled state.
outputs
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Multiple Serial Interface
MSTR
4
0
CPOL
3
0
CPHA
2
1
Serial Peripheral Interface (SPI)
SSOE
1
0
Multiple Serial Interface
Operating
LSBF
Bit 0
0
Technical Data
Modes.
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