mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 34

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Central Processing Unit
2.6 Indexed Addressing Modes
Technical Data
34
rr0nnnnn
111rr0zs
111rr011
rr1pnnnn
111rr1aa
111rr111
Code (xb)
Postbyte
The CPU12 indexed modes reduce execution time and eliminate code
size penalties for using the Y index register. CPU12 indexed addressing
uses a postbyte plus zero, one, or two extension bytes after the
instruction opcode. The postbyte and extensions do the following tasks:
,r
n,r
–n,r
n,r
–n,r
[n,r]
n,–r n,+r
n,r– n,r+
A,r
B,r
D,r
[D,r]
Freescale Semiconductor, Inc.
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Source
Syntax
Code
For More Information On This Product,
Specify which index register is used.
Determine whether a value in an accumulator is used as an offset.
Enable automatic pre- or post-increment or decrement
Specify use of 5-bit, 9-bit, or 16-bit signed offsets.
Table 2-3. Summary of Indexed Operations
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Central Processing Unit
5-bit constant offset n = –16 to +15
rr can specify X, Y, SP, or PC
Constant offset (9- or 16-bit signed)
z-0 = 9-bit with sign in LSB of postbyte(s)
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC
Auto pre-decrement/increment or Auto post-
decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
Accumulator offset (unsigned 8-bit or 16-bit)
aa-00 = A
rr can specify X, Y, SP, or PC
Accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
1 = 16-bit
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
Comments
MC68HC912DG128 — Rev 3.0
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