mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 290

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Inter-IC Bus
15.7 IIC Programming Examples
15.7.1 Initialization Sequence
15.7.2 Generation of START
Technical Data
290
Reset will put the IIC Bus Control Register to its default status. Before
the interface can be used to transfer serial data, an initialization
procedure must be carried out, as follows:
After completion of the initialization procedure, serial data can be
transmitted by selecting the ’master transmitter’ mode. If the device is
connected to a multi-master bus system, the state of the IIC Bus Busy
bit (IBB) must be tested to check whether the serial bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave
address) can be sent. The data written to the data register comprises the
slave calling address and the LSB set to indicate the direction of transfer
required from the slave.
The bus free time (i.e., the time between a STOP condition and the
following START condition) is built into the hardware that generates the
START cycle. Depending on the relative frequencies of the system clock
and the SCL period it may be necessary to wait until the IIC is busy after
writing the calling address to the IBDR before proceeding with the
following instructions. This is illustrated in the following example.
1. Update the Frequency Divider Register (IBFD) and select the
2. Update the IIC Bus Address Register (IBAD) to define its slave
3. Set the IBEN bit of the IIC Bus Control Register (IBCR) to enable
4. Modify the bits of the IIC Bus Control Register (IBCR) to select
Freescale Semiconductor, Inc.
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required division ratio to obtain SCL frequency from system clock.
address.
the IIC interface system.
Master/Slave mode, Transmit/Receive mode and interrupt enable
or not.
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Inter-IC Bus
MC68HC912DG128 — Rev 3.0
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