mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 286

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

IBSR — IIC Bus Status Register
Inter-IC Bus
Technical Data
286
RESET:
Bit 7
TCF
1
IAAS
6
0
TCF — Data transferring bit
IAAS — Addressed as a slave bit
IBB — IIC Bus busy bit
IBAL — Arbitration Lost
1. SDA sampled as low when the master drives a high during an
2. SDA sampled as a low when the master drives a high during the
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
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This status register is read-only with exception of bit 1 (IBIF) and bit 4
(IBAL), which are software clearable
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the 9th clock of a byte transfer.
When its own specific address (IIC Bus Address Register) is matched
with the calling address, this bit is set. The CPU is interrupted
provided the IBIE is set. Then the CPU needs to check the SRW bit
and set its Tx/Rx mode accordingly. Writing to the IIC Bus Control
Register clears this bit.
This bit indicates the status of the bus. When a START signal is
detected, the IBB is set. If a STOP signal is detected, it is cleared.
The arbitration lost bit (IBAL) is set by hardware when the arbitration
procedure is lost. Arbitration is lost in the following circumstances:
For More Information On This Product,
0 = Transfer in progress
1 = Transfer complete
0 = Not addressed
1 = Addressed as a slave
0 = Bus is idle
1 = Bus is busy
address or data transmit cycle.
acknowledge bit of a data receive cycle.
IBB
5
0
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IBAL
4
0
Inter-IC Bus
3
0
0
SRW
2
0
MC68HC912DG128 — Rev 3.0
IBIF
1
0
RXAK
Bit 0
0
MOTOROLA
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