mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 239

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

ICSYS — Input Control System Control Register
MC68HC912DG128 — Rev 3.0
MOTOROLA
RESET:
SH37
BIT 7
0
SH26
6
0
SHxy — Share Input action of Input Capture Channels x and y
TFMOD — Timer Flag-setting Mode
Freescale Semiconductor, Inc.
Read: any time
Write: May be written once (SMODN=1). Writes are always permitted
when SMODN=0.
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with
the use of the ICOVW register ($AA) allows a timer interrupt to be
generated after capturing two values in the capture and holding
registers instead of generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVW bit is set and the
corresponding capture and holding registers are emptied, an input
capture event will first update the related input capture register with
the main timer contents. At the next event the TCn data is transferred
to the TCnH register, The TCn is updated and the CnF interrupt flag
is set. See
In all other input capture cases the interrupt flag is set by a valid
external event on PTn.
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0 = Normal operation
1 = The channel input ‘x’ causes the same action on the channel
0 = The timer flags C3F–C0F in TFLG1 ($8E) are set when a valid
1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags
SH15
5
0
‘y’. The port pin ‘x’ and the corresponding edge detector is
used to be active on the channel ‘y’.
input capture transition on the corresponding port pin occurs.
C3F–C0F in TFLG1 ($8E) are set only when a latch on the
corresponding holding register occurs.
If the queue mode is not engaged, the timer flags C3F–C0F are
set the same way as for TFMOD=0.
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Enhanced Capture Timer
Figure
SH04
4
0
13-6.
TFMOD
3
0
PACMX
2
0
BUFEN
1
0
Enhanced Capture Timer
LATQ
BIT 0
0
Timer Registers
Technical Data
$00AB
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