isp1563 NXP Semiconductors, isp1563 Datasheet - Page 29

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 36.
Address: Value read from address 34h + 4h
[1]
[2]
Table 37.
Address: Value read from address 34h + 4h
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
15
14 to 13
12 to 9
8
7 to 2
Sticky bit, if the function supports PME# from D3
function does not support PME# from D3
The reserved bits should always be written with the reset value.
Symbol
PMES
DS[1:0]
D_S[3:0]
PMEE
reserved
PMCSR - Power Management Control/Status register bit allocation
PMCSR - Power Management Control/Status register bit description
8.2.3.4 PMCSR register
PMES
R/W
R/W
X
15
7
0
[1]
Description
PME Status: This bit is set when the function normally assert the PME# signal independent of the
state of the PMEE bit. Writing logic 1 to this bit clears it and causes the function to stop asserting
PME#, if enabled. Writing logic 0 has no effect. This bit defaults to logic 0, if the function does not
support the PME# generation from D3
then this bit is sticky and must be explicitly cleared by the operating system each time the operating
system is initially loaded.
Data Scale: This two-bit read-only field indicates the scaling factor when interpreting the value of the
Data register. The value and meaning of this field vary, depending on which data value is selected by
the D_S field. This field is a required component of the Data register (offset 7) and must be
implemented, if the Data register is implemented. If the Data register is not implemented, this field
must return 00b when PMCSR is read.
Data Select: This four-bit field selects the data that is reported through the Data register and the
D_S field. This field is a required component of the Data register (offset 7) and must be
implemented, if the Data register is implemented. If the Data register is not implemented, this field
must return 00b when PMCSR is read.
PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is
disabled. This bit defaults to logic 0, if the function does not support the PME# generation from
D3
by the operating system each time the operating system is initially loaded.
-
The logic level of the AMB4 pin at power-on determines the default value of PMC
registers. If this pin is pulled up to 3.3 V, the ISP1563 will report that it supports PME
generation in D3
down, the ISP1563 will report that it does not support PME generation in D3
(PME_S4) will be reset to 0).
The Power Management Control/Status (PMCSR) register is a 2-byte register used to
manage the power management state of the PCI function, as well as to allow and monitor
Power Management Events (PMEs). The bit allocation of the register is given in
cold
. If the function supports PME# from D3
R/W
14
R
0
6
0
DS[1:0]
cold
cold
.
R/W
13
R
0
5
0
(bit 15 (PME_S4) will be set to 1). If this pin is left open or is pulled
cold
reserved
, then X is indeterminate at the time of initial operating system boot; X is 0 if the
Rev. 02 — 15 March 2007
[2]
R/W
R/W
12
0
4
0
cold
. If the function supports the PME# generation from D3
cold
, then this bit is sticky and must explicitly be cleared
R/W
R/W
11
0
3
0
D_S[3:0]
R/W
R/W
10
0
2
0
HS USB PCI Host Controller
R/W
R/W
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1563
PS[1:0]
cold
(bit 15
Table
PMEE
R/W
R/W
X
29 of 102
8
0
0
[1]
cold
36.
,