isp1563 NXP Semiconductors, isp1563 Datasheet - Page 39

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 46.
Address: Content of the base address register + 04h
Table 47.
[1]
ISP1563_2
Product data sheet
Bit
1 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Address: Content of the base address register + 08h
The reserved bits should always be written with the reset value.
HcControl - Host Controller Control register bit description
HcCommandStatus - Host Controller Command Status register bit allocation
Symbol
CBSR[1:0]
11.1.3 HcCommandStatus register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
This register is used by the Host Controller to receive commands issued by the HCD. It
also reflects the current status of the Host Controller. To the HCD, it appears as a ‘write to
set’ register. The Host Controller must ensure that bits written as logic 1 become set in the
register while bits written as logic 0 remain unchanged in the register. The HCD may issue
multiple distinct commands to the Host Controller without concern for corrupting
previously issued commands. The HCD has normal read access to all bits.
The SOC[1:0] field (bits 17 and 16 in the HcCommandStatus register) indicates the
number of frames with which the Host Controller has detected the scheduling overrun
error. This occurs when the periodic list does not complete before EOF. When a
scheduling overrun error is detected, the Host Controller increments the counter and sets
SO (bit 0 in the HcInterruptStatus register). For bit allocation, see
Description
Control Bulk Service Ratio: This specifies the service ratio of control EDs over bulk EDs.
Before processing any of the nonperiodic lists, the Host Controller must compare the ratio
specified with its internal count on how many nonempty control EDs are processed, in
determining whether to continue serving another control ED or switch to bulk EDs. The internal
count must be retained when crossing the frame boundary. After a reset, the HCD is responsible
to restore this value.
00b — 1 : 1
01b — 2 : 1
10b — 3 : 1
11b — 4 : 1
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
reserved
[1]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
reserved
Rev. 02 — 15 March 2007
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
[1]
[1]
OCR
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
…continued
R/W
R/W
R/W
R/W
BLF
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
Table
R/W
R/W
R/W
R/W
CLF
25
17
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
47.
ISP1563
SOC[1:0]
HCR
R/W
R/W
R/W
R/W
39 of 102
24
16
0
0
8
0
0
0