isp1563 NXP Semiconductors, isp1563 Datasheet - Page 44

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
Table 54.
Address: Content of the base address register + 14h
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
31
30
29 to 7 reserved -
6
5
4
3
2
1
0
The reserved bits should always be written with the reset value.
Symbol Description
MIE
OC
RHSC
FNO
UE
RD
SF
WDH
SO
HcInterruptDisable - Host Controller Interrupt Disable register bit description
11.1.7 HcHCCA register
reserved
R/W
7
0
Master Interrupt Enable:
0 — Ignore
1 — Disables interrupt generation because of events specified in other bits of this register.
This field is set after a hardware or software reset. Interrupts are disabled.
Ownership Change:
0 — Ignore
1 — Disables interrupt generation because of ownership change.
Root Hub Status Change:
0 — Ignore
1 — Disables interrupt generation because of root hub status change.
Frame Number Overflow:
0 — Ignore
1 — Disables interrupt generation because of frame number overflow.
Unrecoverable Error:
0 — Ignore
1 — Disables interrupt generation because of unrecoverable error.
Resume Detect:
0 — Ignore
1 — Disables interrupt generation because of resume detect.
Start-of-Frame:
0 — Ignore
1 — Disables interrupt generation because of Start-of-Frame.
Write-back Done Head:
0 — Ignore
1 — Disables interrupt generation because of HcDoneHead write-back.
Scheduling Overrun:
0 — Ignore
1 — Disables interrupt generation because of scheduling overrun.
[1]
The HcHCCA register contains the physical address of Host Controller Communication
Area (HCCA). The bit allocation is given in
restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The
alignment is evaluated by examining the number of zeroes in lower order bits. The
RHSC
R/W
6
0
FNO
R/W
5
0
Rev. 02 — 15 March 2007
R/W
UE
4
0
Table
R/W
RD
3
0
55. The HCD determines alignment
R/W
SF
2
0
HS USB PCI Host Controller
WDH
R/W
1
0
© NXP B.V. 2007. All rights reserved.
ISP1563
R/W
SO
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0
0