isp1563 NXP Semiconductors, isp1563 Datasheet - Page 98

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 53. HcInterruptDisable - Host Controller
Table 54. HcInterruptDisable - Host Controller
Table 55. HcHCCA - Host Controller Communication
Table 56. HcHCCA - Host Controller Communication
Table 57. HcPeriodCurrentED - Host Controller
Table 58. HcPeriodCurrentED - Host Controller Period
Table 59. HcControlHeadED - Host Controller
Table 60. HcControlHeadED - Host Controller
Table 61. HcControlCurrentED - Host Controller
Table 62. HcControlCurrentED - Host Controller
Table 63. HcBulkHeadED - Host Controller Bulk Head
Table 64. HcBulkHeadED - Host Controller Bulk Head
Table 65. HcBulkCurrentED - Host Controller Bulk
Table 66. HcBulkCurrentED - Host Controller Bulk
Table 67. HcDoneHead - Host Controller Done Head
Table 68. HcDoneHead - Host Controller Done Head
Table 69. HcFmInterval - Host Controller Frame
Table 70. HcFmInterval - Host Controller Frame
Table 71. HcFmRemaining - Host Controller Frame
Table 72. HcFmRemaining - Host Controller Frame
Table 73. HcFmNumber - Host Controller Frame
ISP1563_2
Product data sheet
Interrupt Enable register bit description . . . . . .42
Interrupt Disable register bit allocation . . . . . .43
Interrupt Disable register bit description . . . . .44
Area register bit allocation . . . . . . . . . . . . . . . .45
Area register bit description . . . . . . . . . . . . . . .45
Period Current Endpoint Descriptor
register bit allocation . . . . . . . . . . . . . . . . . . . .45
Current Endpoint Descriptor register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Control Head Endpoint Descriptor
register bit allocation . . . . . . . . . . . . . . . . . . . .46
Control Head Endpoint Descriptor
register bit description . . . . . . . . . . . . . . . . . . .47
Control Current Endpoint Descriptor
register bit allocation . . . . . . . . . . . . . . . . . . . .47
Control Current Endpoint Descriptor
register bit description . . . . . . . . . . . . . . . . . . .47
Endpoint Descriptor register bit allocation . . . .48
Endpoint Descriptor register bit description . . .48
Current Endpoint Descriptor
register bit allocation . . . . . . . . . . . . . . . . . . . .48
Current Endpoint Descriptor
register bit description . . . . . . . . . . . . . . . . . . .49
register bit allocation . . . . . . . . . . . . . . . . . . . .49
register bit description . . . . . . . . . . . . . . . . . . .50
Interval register bit allocation . . . . . . . . . . . . . .50
Interval register bit description . . . . . . . . . . . . .51
Remaining register bit allocation . . . . . . . . . . .51
Remaining register bit description . . . . . . . . . .52
Number register bit allocation . . . . . . . . . . . . .52
Rev. 02 — 15 March 2007
Table 74. HcFmNumber - Host Controller
Table 75. HcPeriodicStart - Host Controller
Table 76. HcPeriodicStart - Host Controller
Table 77. HcLSThreshold - Host Controller
Table 78. HcLSThreshold - Host Controller
Table 79. HcRhDescriptorA - Host Controller Root
Table 80. HcRhDescriptorA - Host Controller Root
Table 81. HcRhDescriptorB - Host Controller Root
Table 82. HcRhDescriptorB - Host Controller Root
Table 83. HcRhStatus - Host Controller Root Hub
Table 84. HcRhStatus - Host Controller Root Hub
Table 85. HcRhPortStatus[4:1] - Host Controller Root
Table 86. HcRhPortStatus[4:1] - Host Controller Root
Table 87. Legacy support registers . . . . . . . . . . . . . . . . . 61
Table 88. Emulated registers . . . . . . . . . . . . . . . . . . . . . 61
Table 89. HceControl - Host Controller Emulation
Table 90. HceControl - Host Controller Emulation
Table 91. HceInput - Host Controller Emulation
Table 92. HceInput - Host Controller Emulation
Table 93. HceOutput - Host Controller Emulation
Table 94. HceOutput - Host Controller Emulation
Table 95. HceStatus - Host Controller Emulation
Table 96. HceStatus - Host Controller Emulation
Table 97. CAPLENGTH/HCIVERSION - Capability
Table 98. CAPLENGTH/HCIVERSION - Capability
Frame Number register bit description . . . . . . 52
Periodic Start register bit allocation . . . . . . . . . 53
Periodic Start register bit description . . . . . . . 53
LS Threshold register bit allocation . . . . . . . . . 53
Low-Speed Threshold register
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 54
Hub Descriptor A register bit allocation . . . . . . 54
Hub Descriptor A register bit description . . . . . 55
Hub Descriptor B register bit allocation . . . . . . 56
Hub Descriptor B register bit description . . . . . 56
Status register bit allocation . . . . . . . . . . . . . . 57
Status register bit description . . . . . . . . . . . . . 57
Hub Port Status[4:1] register bit allocation . . . 58
Hub Port Status[4:1] register bit description . . 59
Control register bit allocation . . . . . . . . . . . . . . 62
Control register bit description . . . . . . . . . . . . 62
Input register bit allocation . . . . . . . . . . . . . . . 63
Input register bit description . . . . . . . . . . . . . . 63
Output register bit allocation . . . . . . . . . . . . . . 64
Output register bit description . . . . . . . . . . . . . 64
Status register bit allocation . . . . . . . . . . . . . . 64
Status register bit description . . . . . . . . . . . . . 65
Length/Host Controller Interface Version
Number register bit allocation . . . . . . . . . . . . . 66
Length/Host Controller Interface Version
Number register bit description . . . . . . . . . . . . 66
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1563
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