isp1563 NXP Semiconductors, isp1563 Datasheet - Page 75

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 110. FRINDEX - Frame Index register bit description
Address: Content of the base address register + 2Ch
Table 112. PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation
Address: Content of the base address register + 34h
ISP1563_2
Product data sheet
Bit
31 to 14
13 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
reserved
FRINDEX
[13:0]
11.4.5 PERIODICLISTBASE register
R/W
R/W
R/W
31
23
15
0
0
0
Description
-
Frame Index: Bits in this register are used for the frame number in the SOF packet and as the index
into the frame list. The value in this register increments at the end of each time frame. For example,
microframe. The bits used for the frame number in the SOF token are taken from bits 13 to 3 of this
register. Bits N to 3 are used for the frame list current index. This means that each location of the
frame list is accessed eight times, frames or microframes, before moving to the next index.
illustrates values of N based on the value of FLS[1:0] (bits 3 to 2 in the USBCMD register).
Table 111. N based value of FLS[1:0]
The Periodic Frame List Base Address (PERIODLISTBASE) register contains the
beginning address of the periodic frame list in the system memory. If the Host Controller is
in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 in the HCCPARAMS register), the
most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register. For details on the CTRLDSSEGMENT register, refer to
Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 . The
system software loads this register before starting the schedule execution by the Host
Controller. The memory structure referenced by this physical memory pointer is assumed
as 4 kB aligned. The contents of this register are combined with the FRINDEX register to
enable the Host Controller to step through the periodic frame list in sequence.
The bit allocation is given in
FLS[1:0]
00b
01b
10b
11b
R/W
R/W
R/W
30
22
14
0
0
0
BA[3:0]
R/W
R/W
R/W
29
21
13
0
0
0
Rev. 02 — 15 March 2007
Table
Number elements
1024
512
256
reserved
R/W
R/W
R/W
28
20
12
0
0
0
112.
BA[19:12]
BA[11:4]
R/W
R/W
R/W
27
19
11
0
0
0
R/W
R/W
R/W
26
18
10
0
0
0
HS USB PCI Host Controller
reserved
N
12
11
10
-
[1]
R/W
R/W
R/W
25
17
0
0
9
0
© NXP B.V. 2007. All rights reserved.
ISP1563
Table 111
R/W
R/W
R/W
75 of 102
24
16
0
0
8
0