isp1563 NXP Semiconductors, isp1563 Datasheet - Page 31

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 41.
Address: Value read from address 34h + 7h
Legend: * reset value
9. I
ISP1563_2
Product data sheet
Bit
7 to 0
2
C-bus interface
Symbol
DATA[7:0]
DATA - Data register bit description
8.2.3.6 Data register
9.1 Protocol
Access
R
Table 40.
[1]
The Data register is an optional, 1-byte register that provides a mechanism for the
function to report state dependent operating data, such as power consumed or heat
dissipated.
A simple I
product ID and some other configuration bits from an external EEPROM.
The I
wires: SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must
be connected to the positive supply voltage through pull-up resistors, when in use;
otherwise, they must be connected to ground.
The I
Each device on the I
device for access.
The master starts a data transfer using a START condition and ends it by generating a
STOP condition. Transfers can only be initiated when the bus is free. The receiver must
acknowledge each byte by using a LOW level on SDA during the ninth clock pulse on
SCL.
For detailed information, refer to The I
Originating device’s
bridge PM state
D3
D3
•
•
•
•
hot
cold
PM: Power Management.
Bus free: both SDA and SCL are HIGH
START: a HIGH-to-LOW transition on SDA, while SCL is HIGH
STOP: a LOW-to-HIGH transition on SDA, while SCL is HIGH
Data valid: after a START condition, data on SDA is stable during the HIGH period of
SCL; data on SDA may only change while SCL is LOW
2
2
C-bus interface is for bidirectional communication between ICs using two serial bus
C-bus protocol defines the following conditions:
Value Description
00h*
2
PCI bus power and clock control
C-bus interface is provided in the ISP1563 to read customized vendor ID,
Table 41
DATA: This register is used to report the state dependent data requested by the
D_S field of the PMCSR register. The value of this register is scaled by the value
reported by the DS field of the PMCSR register.
[1]
2
shows the bit description of the register.
C-bus has a unique slave address, which the master uses to select a
Secondary bus
PM state
B2, B3
B3
Rev. 02 — 15 March 2007
[1]
Resultant actions by bridge (either direct or indirect)
clock stopped and PCI V
bus (B3 only); for definition of B2_B3#, see
none
2
C-bus Specification Version 2.1 .
…continued
HS USB PCI Host Controller
CC
removed from secondary
© NXP B.V. 2007. All rights reserved.
ISP1563
Table
31 of 102
39.