isp1563 NXP Semiconductors, isp1563 Datasheet - Page 68

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 101. HCCPARAMS - Host Controller Capability Parameters register bit allocation
Address: Content of the base address register + 08h
Table 102. HCCPARAMS - Host Controller Capability Parameters register bit description
Address: Content of the base address register + 08h
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7 to 4
3 to 2
1
0
Symbol
reserved
IST[3:0]
reserved
PFLF
64AC
11.3.3 HCCPARAMS register
11.3.4 HCSP-PORTROUTE register
31
23
15
R
R
R
R
0
0
0
7
0
The Host Controller Capability Parameters (HCCPARAMS) register is a 4-byte register,
and the bit allocation is given in
The HCSP-PORTROUTE (Companion Port Route Description) register is an optional
read-only field that is valid only if PRR (bit 7 in the HCSPARAMS register) is logic 1. Its
address is content of the base address register + 0Ch.
Description
-
Isochronous Scheduling Threshold: Default = implementation-dependent. This field indicates,
relative to the current position of the executing Host Controller, where software can reliably
update the isochronous schedule. When IST[3] is logic 0, the value of the least significant three
bits indicates the number of microframes a Host Controller can hold a set of isochronous data
structures, one or more, before flushing the state. When IST[3] is logic 1, the host software
assumes the Host Controller may cache an isochronous data structure for an entire frame.
-
Programmable Frame List Flag: Default = implementation-dependent. If this bit is cleared, the
system software must use a frame list length of 1024 elements with the Host Controller. The
USBCMD register FLS[1:0] (bits 3 and 2) is read-only and must be cleared. If PFLF is set, the
system software can specify and use a smaller frame list, and configure the host through the FLS
bit. The frame list must always be aligned on a 4 kB page boundary to ensure that the frame list is
always physically contiguous.
64-bit Addressing Capability: This field contains the addressing range capability.
0 — Data structures using 32-bit address memory pointers.
1 — Data structures using 64-bit address memory pointers.
30
22
14
R
R
R
R
0
0
0
6
0
IST[3:0]
29
21
13
R
R
R
R
0
0
0
5
0
Rev. 02 — 15 March 2007
Table
28
20
12
R
R
R
R
0
0
0
4
1
reserved
reserved
reserved
101.
27
19
11
R
R
R
R
0
0
0
3
0
reserved
26
18
10
R
R
R
R
0
0
0
2
0
HS USB PCI Host Controller
PFLF
25
17
R
R
R
R
0
0
9
0
1
1
© NXP B.V. 2007. All rights reserved.
ISP1563
64AC
68 of 102
24
16
R
R
R
R
0
0
8
0
0
0