isp1563 NXP Semiconductors, isp1563 Datasheet - Page 70

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 104. USBCMD - USB Command register bit description
Address: Content of the base address register + 20h
ISP1563_2
Product data sheet
Bit
23 to 16
15 to 8
7
6
5
4
3 to 2
Symbol
ITC[7:0]
reserved
LHCR
IAAD
ASE
PSE
FLS[1:0]
Description
Interrupt Threshold Control: Default = 08h. This field is used by the system software to select
the maximum rate at which the Host Controller will issue interrupts. If software writes an invalid
value to this register, the results are undefined. Valid values are:
00h — reserved
01h — 1 microframe
02h — 2 microframes
04h — 4 microframes
08h — 8 microframes (equals 1 ms)
10h — 16 microframes (equals 2 ms)
20h — 32 microframes (equals 4 ms)
40h — 64 microframes (equals 8 ms)
Software modifications to this field while HCH (bit 12 in the USBSTS register) is zero results in
undefined behavior.
-
Light Host Controller Reset: This control bit is not required. It allows the driver software to reset
the EHCI controller, without affecting the state of the ports or the relationship to the companion
Host Controllers. If not implemented, a read of this field will always return zero. If implemented,
on read:
0 — Indicates that the Light Host Controller Reset has completed and it is ready for the host
software to re-initialize the Host Controller.
1 — Indicates that the Light Host Controller Reset has not yet completed.
Interrupt on Asynchronous Advance Doorbell: This bit is used as a doorbell by software to
notify the Host Controller to issue an interrupt the next time it advances the asynchronous
schedule. Software must write logic 1 to this bit to ring the doorbell. When the Host Controller has
evicted all appropriate cached schedule states, it sets IAA (bit 5 in the USBSTS register). If IAAE
(bit 5 in the USBINTR register) is logic 1, then the Host Controller will assert an interrupt at the
next interrupt threshold. The Host Controller sets this bit to logic 1 after it sets IAA. Software must
not set this bit when the asynchronous schedule is inactive because this results in an undefined
value.
Asynchronous Schedule Enable: Default = 0. This bit controls whether the Host Controller
skips processing the asynchronous schedule.
0 — Do not process the asynchronous schedule.
1 — Use the ASYNCLISTADDR register to access the asynchronous schedule.
Periodic Schedule Enable: Default = 0. This bit controls whether the Host Controller skips
processing the periodic schedule.
0 — Do not process the periodic schedule.
1 — Use the PERIODICLISTBASE register to access the periodic schedule.
Frame List Size: Default = 00b. This field is read and write only if PFLF (bit 1 in the
HCCPARAMS register) is set to logic 1. This field specifies the size of the frame list. The size the
frame list controls which bits in the Frame Index register must be used for the frame list current
index.
00b — 1024 elements (4096 bytes)
01b — 512 elements (2048 bytes)
10b — 256 elements (1024 bytes) for small environments
11b — reserved
Rev. 02 — 15 March 2007
…continued
HS USB PCI Host Controller
© NXP B.V. 2007. All rights reserved.
ISP1563
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