isp1563 NXP Semiconductors, isp1563 Datasheet - Page 55

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
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Table 80.
Address: Content of the base address register + 48h
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
31 to 24
23 to 13
12
11
10
9
8
7 to 0
The reserved bits should always be written with the reset value.
X is 1 for OHCI1 (2P) and OHCI2 (2P); X is 0 for OHCI1 (1P) and OHCI2 (1P).
X is 0 for OHCI1 (2P) and OHCI2 (2P); X is 1 for OHCI1 (1P) and OHCI2 (1P).
Symbol
POTPGT
[7:0]
reserved -
NOCP
OCPM
DT
NPS
PSM
NDP[7:0] Number Downstream Ports: These bits specify the number of downstream ports supported by the
HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description
11.1.20 HcRhDescriptorB register
R
7
0
Description
Power On To Power Good Time: This byte specifies the duration the HCD must wait before
accessing a powered-on port of the Root Hub. It is implementation-specific. The unit of time is 2 ms.
The duration is calculated as POTPGT
No Overcurrent Protection: This bit describes how the overcurrent status for root hub ports are
reported. When this bit is cleared, the OCPM bit specifies global or per-port reporting.
0 — Overcurrent status is collectively reported for all downstream ports.
1 — No overcurrent protection supported.
Overcurrent Protection Mode: This bit describes how the overcurrent status for root hub ports are
reported. At reset, this fields reflects the same mode as Power Switching Mode. This field is valid only
if the NOCP bit is cleared.
0 — Overcurrent status is collectively reported for all downstream ports.
1 — Overcurrent status is reported on a per-port basis.
Device Type: This bit specifies that the root hub is not a compound device. The root hub is not
permitted to be a compound device. This field must always read logic 0.
No Power Switching: This bit is used to specify whether power switching is supported or ports are
always powered. It is implementation-specific. When this bit is cleared, the PSM bit specifies global or
per-port switching.
0 — Ports are power switched.
1 — Ports are always powered on when the Host Controller is powered on.
Power Switching Mode: This bit is used to specify how the power switching of root hub ports is
controlled. It is implementation-specific. This field is valid only if the NPS bit is cleared.
0 — All ports are powered at the same time.
1 — Each port is individually powered. This mode allows port power to be controlled by either the
global switch or per-port switching. If the PPCM (Port Power Control Mask) bit is set, the port
responds only to port power commands (Set/Clear Port Power). If the port mask is cleared, then the
port is controlled only by the global power switch (Set/Clear Global Power).
root hub. It is implementation-specific. The minimum number of ports is 1. The maximum number of
ports supported by OHCI is 15.
The HcRhDescriptorB register (see
characteristics of the root hub. These fields are written during initialization to correspond
to the system implementation. Reset values are implementation-specific.
R
6
0
R
5
0
Rev. 02 — 15 March 2007
R
4
0
2 ms.
NDP[7:0]
Table
81) is the second of two registers describing the
R
3
0
R
2
0
HS USB PCI Host Controller
X
R
1
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© NXP B.V. 2007. All rights reserved.
ISP1563
X
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R
0
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