isp1563 NXP Semiconductors, isp1563 Datasheet - Page 65

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
Table 96.
Address: Content of the base address register + 10Ch
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7
6
5
4
3
2
1
0
The reserved bits should always be written with the reset value.
Symbol
reserved
PARITY
TIMEOUT
AUX_OUT_
FULL
INH_SW
CMD_DATA
FLAG
IN_FULL
OUT_FULL
HceStatus - Host Controller Emulation Status register bit description
11.3.1 CAPLENGTH/HCIVERSION register
PARITY
11.3 EHCI controller capability registers
R/W
R/W
R/W
23
15
0
0
7
0
Description
-
Parity: This bit indicates parity error on keyboard and mouse data.
Time-out: This bit indicates a time-out.
Auxiliary Output Full: IRQ12 is asserted whenever this bit is set to logic 1, OUT_FULL is set to
logic 1, and the IRQEN bit is set.
Inhibit Switch: This bit reflects the state of the keyboard inhibit switch. If set, the keyboard is
active.
Cmd Data: The Host Controller sets this bit to logic 0 on an I/O write to port 60h and to logic 1 on
an I/O write to port 64h.
Flag: Nominally used as a system flag by software to indicate a warm or cold boot.
Input Full: Except in the case of a gate A20 sequence, this bit is set to logic 1 on an I/O write to
address 60h or 64h. While this bit is set to logic 1 and emulation is enabled, an emulation interrupt
condition exists.
Output Full: The Host Controller sets this bit to logic 0 on a read of I/O port 60h. If IRQEN is set,
AUX_OUT_FULL determines which IRQ is activated. While this bit is logic 0 and C_P in HceControl
is set to logic 1, an emulation interrupt condition exists.
Other than the OHCI Host Controller, there are some registers in EHCI that define the
capability of EHCI. The address range of these registers is located before the operational
registers.
The bit allocation of this 4-byte register is given in
TIMEOUT
R/W
R/W
R/W
22
14
0
0
6
0
AUX_OUT_
FULL
R/W
R/W
R/W
21
13
0
0
5
0
Rev. 02 — 15 March 2007
INH_SW
R/W
R/W
R/W
20
12
0
0
4
0
reserved
reserved
[1]
[1]
CMD_
DATA
R/W
R/W
R/W
19
11
0
0
3
0
Table
FLAG
R/W
R/W
R/W
97.
18
10
0
0
2
0
HS USB PCI Host Controller
IN_FULL
R/W
R/W
R/W
17
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1563
OUT_FULL
R/W
R/W
R/W
65 of 102
16
0
8
0
0
0