isp1563 NXP Semiconductors, isp1563 Datasheet - Page 78

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 118. PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit allocation
Address: Content of the base address register + 64h + (4
[1]
Table 119. PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description
Address: Content of the base address register + 64h + (4
ISP1563_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 23
22
21
20
19 to 16
The reserved bits should always be written with the reset value.
Symbol
reserved
WKOC_E
WKDS
CNNT_E
WKCNNT_E Wake on Connect Enable: Default = 0. Setting this bit enables the port to be sensitive to device
PTC[3:0]
reserved
SUSP
R/W
R/W
R/W
31
23
15
R
0
0
0
7
0
PIC[1:0]
[1]
If the port has power control, software cannot change the state of the port until it sets port
power bits. Software must not attempt to change the state of the port until power is stable
on the port; maximum delay is 20 ms from the transition. For bit allocation, see
Description
-
Wake on Overcurrent Enable: Default = 0. Setting this bit enables the port to be sensitive to
overcurrent conditions as wake-up events.
Wake on Disconnect Enable: Default = 0. Setting this bit enables the port to be sensitive to
device disconnects as wake-up events.
connects as wake-up events.
Port Test Control: Default = 0000b. When this field is logic 0, the port is not operating in test
mode. A nonzero value indicates that it is operating in test mode and test mode is indicated by the
value. The encoding of the test mode bits are:
0000b — Test mode disabled
0001b — Test J_STATE
0010b — Test K_STATE
0011b — Test SE0_NAK
0100b — Test packet
0101b — Test FORCE_ENABLE
0110b to 1111b — reserved
•
WKOC_E
Port disabled
FPR
R/W
R/W
R/W
30
22
14
R
0
0
0
6
0
CNNT_E
WKDS
OCC
R/W
R/W
R/W
PO
29
21
13
R
0
0
1
5
0
Rev. 02 — 15 March 2007
[1]
WKCNNT_
Port Number
OCA
Port Number
R/W
R/W
R/W
PP
28
20
12
R
E
0
0
0
4
0
reserved
[1]
[1]
[1]
PEDC
R/W
R/W
R/W
R/W
27
19
11
1) where Port Number is 1, 2, 3, 4
1) where Port Number is 1, 2, 3, 4
0
0
0
3
0
LS[1:0]
PED
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
PTC[3:0]
reserved
ECSC
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1563
[1]
Table
ECCS
R/W
R/W
PR
78 of 102
24
16
R
R
0
0
8
0
0
0
118.